3DIO IP For Multi-Die Integration – SemiEngineering
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Accelerate the scaling of system functionality with 3D packaging. The post 3DIO IP For Multi-Die Integration appeared first on Semiconductor Engineering.
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Live from IMAPS Symposium 2024: Updates on the NAPMP, Silicon Photonics and RDL Packaging
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Send us a text This episode was recorded live at the IMAPS International Symposium in Boston MA. Françoise von Trapp speaks with Dev Palmer, director of the National Advanced Packaging Manufacturing Program; Sandeep Sane of Lightmatter; Craig Bishop, Deca and Brett Wilkerson, AMD. Dev Palmer explains Chips Act’s funding distribution and its impact on the […]
Maximizing 3DIC Design Productivity with 3DBlox – SemiWiki
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At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the… Read More The post Maximizing 3DIC Design […]
SEMI Sets Sights on Security – EE Times
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The SEMI SMCC will develop a semiconductor manufacturing industry profile for NIST Cybersecurity Framework 2.0. The post SEMI Sets Sights on Security appeared first on EE Times.
Lam Research’s Chee Ping Lee Explains the Role of HBM in Generative AI
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Send us a text In this episode, Françoise von Trapp speaks with Chee Ping Lee, of Lam Research, about the critical role of high bandwidth memory (HBM) in generative AI, emphasizing its high bandwidth and compact design. HBM memory has received a lot of attention as one of the first technologies to implement 2.5D and […]
Barriers To Chiplet Sockets – SemiEngineering
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Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time to slow down and make real progress. The post Barriers To Chiplet Sockets appeared first on Semiconductor Engineering.
Global Semiconductor Packaging Material Market Outlook Shows Return to Growth – Semiconductor Digest
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Powered by strong semiconductor demand across diverse end applications, the global semiconductor packaging materials market is expected to start a growth cycle with a 5.6% compound annual growth rate (CAGR) projected through 2028. Global Semiconductor Packaging Material Market Outlook Shows Return to Growth Starting in 2024 was posted by Shannon Davis on Semiconductor Digest.
Emerging Technologies Driving Heterogeneous Integration – SemiEngineering
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New architectures, opportunities, and challenges as chipmakers move from monolithic architectures to chiplets. The post Emerging Technologies Driving Heterogeneous Integration appeared first on Semiconductor Engineering.
Revamping the Semiconductor Industry with Hybrid Bonding – EE Times
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The technology promises higher performance and efficiency with lower power consumption. The post Revamping the Semiconductor Industry with Hybrid Bonding appeared first on EE Times.
So You Want To Be an Interconnectologist? A Conversation with Simon McElrea of LQDX
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Send us a text In this episode, Francoise speaks with Simon McElrea, an interconnectologist, about his career in and the evolution of interconnectology, emphasizing its importance in semiconductor packaging. McElrea discusses his roles at semiconductor start-ups like Vertical Circuits and Invensas; his foray into wireless charging at Energous and FreePower; and his return to the […]
What Comes After HBM For Chiplets? – SemiEngineering
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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible? The post What Comes After HBM For Chiplets appeared first on Semiconductor Engineering.
Are Apple’s Mobile Chips Now Made in the U.S? – Tom’s Hardware
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TSMC’s Fab 21 in Arizona already produces A16 processors on the N4P node.
Monita Pau and Jiangtao Hu Talk About Addressing The Challenges of Metrology for Advanced Packaging
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Send us a text In this episode, Françoise von Trapp talks with Onto Innovation’s Monita Pau and Jiangtao Hu about metrology for advanced packaging – why do we need it? What are the challenges, and how do we solve them? In semiconductor manufacturing front-end processes, metrology has always been a critical step to ensure consistency […]
Intel’s CHIPS Act Fund Delayed by Officials – Tom’s Hardware
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Intel’s CHIPS Act funds are reportedly being delayed as Washington requests a more concrete manufacturing roadmap from the company.
Material Export Restrictions Poised to Strain Semiconductors – Semiconductor Digest
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TECHCET has identified a potential strain on US semiconductor manufacturing capability as Chinese export restrictions on key materials have been announced. Material Export Restrictions Poised to Strain Semiconductors was posted by Shannon Davis on Semiconductor Digest.
Tarak Railkar and Benson Chan Preview IMAPS Symposium 2024
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Send us a text In this episode, Tarak Railkar and Benson Chan join Françoise von Trapp for a preview of The IMAPS International Symposium 2024, which takes place in Boston from September 30 to October 3, 2024. This year’s symposium focuses on heterogeneous integration for paradigm-shifting microelectronics and photonics. It will feature a five-track technical […]
Intel and Cadence Collaborate to Advance the All-Important UCIe Standard – SemiWiki
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The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More The post […]
Bruce Kim of SurplusGLOBAL: The Impact of the CHIPS Act on the Secondary Equipment Market
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Send us a text In this episode, Françoise von Trapp speaks with Bruce Kim, of SurplusGLOBAL, for an update on the semiconductor secondary equipment market, and how the US. and European Chips Acts are impacting it. They also discuss the trend of top-tier OEMS prioritizing the development of innovative technology rather than investing in legacy […]
UC Riverside team develops new superconductor material for quantum computing – Tom’s Hardware
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This new superconductor could potentially reduce errors in quantum computers. https://www.tomshardware.com/tech-industry/quantum-computing/uc-riverside-team-develops-new-superconductor-material-for-quantum-computing
Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability – Semiconductor Engineering
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A UCIe case study. The post Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability appeared first on Semiconductor Engineering.
