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Experts at the Table: The impact of optics, copper hybrid bonding, more standardized interconnects, and many other technologies under development. The post Challenges With Chiplets And Packaging appeared first on Semiconductor Engineering.
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I’ve attended the DAC conference and trade show since the late 1980s, and every visit has been a continuing learning experience about the EDA, IP and semiconductor industry. I first started attended as an EDA vendor in 1987, and since 2004 as a freelance marketing professional. There’s a significant amount of preparation… Read More The […]
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In a global industry that relies heavily on collaboration, COVID 19 created a big pause and pivot in one of the key business development tools of the microelectronics industry: technology conferences and trade shows. In this podcast, we’re talking to several industry event organizers to get their take on the past year of what worked, […]
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Many electronic devices today are dependent on semiconductor logic circuits based on switches hard-wired to perform predefined logic functions. Physicists from the National University of Singapore (NUS), together with an international team of researchers, have developed a novel molecular memristor, or an electronic memory device, that has exceptional memory reconfigurability. NUS Researchers Develop Brain-Inspired Memory […]
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How the new test data standard can make the test floor more accessible in real-time. The post Making Test Transparent With Better Data appeared first on Semiconductor Engineering.
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The only thing slowing graphics chip shipments is a supply chain hangover. The post GPU Demand Defies Pre-Pandemic Seasonality appeared first on EETimes.
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SUSS MicroTec SE and SET announce a partnership in sequential die-to-wafer (D2W) hybrid bonding, a die-based interconnect technology. As part of the partnership, SUSS MicroTec and SET will provide a fully automated, customizable, highest-yield equipment solution to customers. This solution will accelerate the industry’s path towards advanced 3D multi-die solutions such as stacked memory and […]
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3D and heterogeneous system integration research including capillary self-assembly of tiny dies with a size of less than 0.1 mm & advanced FHE using FOWLP. The post Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE appeared first on Semiconductor Engineering.
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A new report predicts that the global semiconductor packaging market will reach $60.44 billion by 2030 from $27.10 billion in 2020, growing at a CAGR of 9.10% from 2021 to 2030. Semiconductor Packaging Market to Reach $60.44B by 2030 was posted by Pete Singer on Semiconductor Digest.
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Over the last 18 months, the European semiconductor industry has felt the repercussions of supply chain interruptions due COVID 19 and trade wars, combined with exploding global demand for chips driven by the digital transformation. There are also questions about regional sovereignty and the need to strengthen the local supply chain. To address these topics […]
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At SEMICON Southeast Asia 2021, Mr. Terence Gan, SVP, Semiconductors, Economic Development Board (EDB) of Singapore, outlined five research pillars. Singapore’s Five Research Pillars Outlined at SEMICON Southeast Asia was posted by Pete Singer on Semiconductor Digest.
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Over the last 50 years, global temperatures have risen due to increased greenhouse gas emissions. A shared commitment and technological innovation can help reverse the impact of climate change. The post Renewable Energy, Tech Innovation Needed to Slow Climate Change appeared first on EETimes.
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The benefits of WLFO versus flip-chip land grid array (FCLGA) packaging for a radio frequency (RF) MEMS digital tunable capacitor array. The post Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS appeared first on Semiconductor Engineering.
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Arizona, New York and Texas are in the running, with U.S. tax breaks likely the deciding factor. The post Samsung Considering 3 U.S. Fab Locations appeared first on EETimes.
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Experts at the Table: Rising costs and the physical limits of reticles is forcing more companies to examine alternatives to shrinking geometries. The post Current And Future Packaging Trends appeared first on Semiconductor Engineering.
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Wet process offers edge etch and clean to improve wafer yield with high throughput and low chemical consumption; First tool expected to ship during third quarter of 2021 ACM Research, a supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging applications, announced the launch of its Bevel Etch product, which further expands ACM’s […]
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The acronyms involving funding for semiconductor manufacturing are flying around Washington. There is the Chips for America Act, focused on re-shoring, The Facilitating American-Built Semiconductors (FABS) Act that promises tax credits for investments in, either equipment or fabs. and then there’s the $250 billion US Innovation and Competition Act, which earmarks $52bn for new chip […]
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Highlights • Amkor is advancing the evolution of 5G RF module design • Amkor DSMBGA enables integration of more components • The advanced packaging market for 5G RF Front End Module (FEM) projected to reach US $2.3B by 2026 • Amkor continues to innovate in advanced SiP technologies Amkor Technology, Inc. (Nasdaq: AMKR), a leading […]
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Sales in June were 2.1% more than the May 2021 total of $43.6 billion. Global Semiconductor Sales Increase 29.2% Year-to-Year in June; Q2 Sales Up 8.3% Over Q1 was posted by Shannon Davis on Semiconductor Digest.
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Earlier this year, on February 18, 2021, the next-generation Mars Rover, Perseverance, successfully landed on Mars. According to Earth and Sky Magazine, Perseverance was the first artificial object to land on Mars since 2018, and the first Rover to land since 2012 when Curiosity touched down. Perseverance traveled 293 million miles (472 million km) – […]
