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The 12th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition (IWLPC) brings together some of the semiconductor industry’s most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging.
This year’s event features a number of special events focused on 3D integration including:
- Keynote address by Sitaram Arkalgud, VP, 3D Porfolio & Technologies at Invensas
2.5D/3D IC – Examining Low Cost Alternatives Wednesday, October 14, 2015
2.5D and 3D products have entered the semiconductor market, albeit at the higher end of performance and pricing. The penetration has been slow, primarily due to the high cost of Si interposer technology, and, consequently, new TSV-less technologies have recently been proposed. This presentation will examine the market dynamics, the segments where TSV based products have made significant inroads, and where alternative technologies could have an impact.
- Panel Discussion : Interposers, 3D TSVs, and Alternatives: What are the Options and Where do They Fit?
Moderator: Françoise von Trapp, 3D InCites, Wednesday, October 14, 2015
After years of development and speculation, TSV-based silicon interposer and 3D IC devices are finally being implemented in production volumes in devices destined for high-end computing applications, where the cost/performance benefits are justified. In parallel, many companies have elected to invest in alternative approaches to Si and TSVs to come up with more cost-sensitive solutions to meet the high-density requirements of next-generation mobile products. With the plethora of device types differentiated only by processes flows and materials used, it’s difficult to differentiate between these options and where they are best suited. This interactive panel will attempt to sort out the confusion. With the aid of a Kahoot quiz, we will test the audience’s understanding of available options (there will be right and wrong answers this time, and a prize to the winner) and panelists will fill in the blanks with details on their understanding of the requirements and which device suits which application.
Additionally, there will be 2 special events focused on Fan-Out Wafer Level Packaging:
- Keynote Address by Rama Alapati, Director, Package Architecture & Customer Technology (PACT) at GLOBALFOUNDRIES
High Density Fan-Out: Evolution or Revolution Tuesday, October 13, 2015
Continued form factor and IO density scaling pressures have necessitated innovation in wafer level packaging technologies including High Density Fan-Out at leading edge Si nodes. A thorough analysis of the end applications reveal clear IO density envelopes for multi-die Fan-Out packages. Industry solutions of today are very fragmented, enabling disruption in the application space. Silicon Foundries entry in to the Fan-Out space also clearly highlights opportunities for value capture in this expanding package format. For traditional players in this field “collaborative competition” enables a new way of competing with the foundries and business models that enables this new paradigm are possible and viable.
- Panel Discussion: Fan-Out WLP Panel Processing: Will it Happen and What Will it Be?
Moderator: E. Jan Vardaman, President, TechSearch International, Inc., Tuesday, October 13, 2015
With the demand for thin packages handling devices with increasing I/O counts a number of companies have selected fan-out wafer level packages (FO-WLPs) to meet their needs. The drive to reduce cost has resulted in the investigation of larger scale panel processing for FO-WLPs. The idea is that processing in a larger panel would provide a lower cost structure than a wafer format. A number of new processes are being considered and will be discussed. This panel discussion will also examine some of the issues in large panel processing such as die placement accuracy and speed, molding materials and processes, warpage, and material requirements.
For technical session details, and to register, visit the IWLPC Website.
