The IEEE International Workshop on Chiplet Interconnect Test and Repair (CITaR) focuses exclusively on the test and repair of interconnects for chiplet-based, three-dimensional stacked ICs, and the on-chip infrastructure enabling that. These ICs include so-called 2.5D-, 3D-, and 5.5D-stacked ICs. Die-to-die interconnects might contain micro-bump pairs, hybrid bonds, interposer wires, and through-silicon vias (TSVs). While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form-factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing and repairing their inter-die interconnects. The CITaR workshop offers a unique forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
The CITaR workshop will take place in conjunction with the IEEE European Test Symposium (ETS) in the Swissôtel in Tallinn, Estonia and is technically sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.
Workshop Program
- Keynote Address by Nitza Basoco, Technology and Market Strategist at Teradyne (U.S.)
- Five sessions encompassing 11 paper presentations
- A panel session, titled A Path to DfT Interoperability for 3D
- Social functions: A welcome reception followed by a workshop dinner on day 1 and a lunch on day 2
Learn more: https://ets2025.taltech.ee/index.php?page=110
