The first IEEE International Workshop on Chiplet Interconnect Test and Repair (CITaR) focuses exclusively on the test and repair of interconnects for chiplet-based, three-dimensional stacked ICs, and the on-chip infrastructure that enables that. These ICs include so-called 2.5D-, 3D-, and 5.5D-stacked ICs. Die-to-die interconnects might contain micro-bump pairs, hybrid bonds, interposer wires, and through-silicon vias (TSVs). While these stacked ICs offer many attractive advantages with respect to heterogeneous integration, small form factor, high bandwidth and performance, and low power dissipation, there are many open issues with respect to testing and repairing their inter-die interconnects. The CITaR Workshop offers a unique forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
The CITaR Workshop will take place in conjunction with the IEEE European Test Symposium (ETS) in the Marriott Hotel in The Hague in the Netherlands and is technically sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.
