Mark your calendars for the Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-TEST, held in conjunction with ITC / Test Week 2014, October 23 and 24, 2014 in Seattle, WA
The 3D TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike. 3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.
Workshop Program
- Keynote Address: “3D Rock from the Sun” by Brion Keller, Senior Architect Encounter Test at Cadence Design System.
- Two sessions totaling seven paper presentations
- Two panel-discussion sessions;
- “3D Memories: What Is Coming And How Are We Going To Test That?”, Moderator: Françoise von Trapp, Queen of 3D, 3DInCites. Panelists:
- Jonathon E. Colburn – Principal DfT Engineer – nVidia, USA
- Gary Fleeman – Industry Expert – USA
- Marc Greenberg – Director Product Marketing – Synopsys, USA
- Bob Patti – CTO – Tezzaron Semiconductor, USA
- Betty Prince – CEO – Memory Strategies Internationa, USA
- “2.5D-SICs: Do We Need To Test The Interposer, And If So, How?”, Moderator: Jan Vardaman – President – TechSearch International, USA. Panelists
- Sandeep K. Goel – Academician/Senior Manager – TSMC, USA
- Said Hamdioui – Associate Professor – TU Delft, the Netherlands
- Gerard John – Technical Director Test Dvlpmnt – Amkor Technologies, USA
- Choon-Leong Lou – CEO – STAr Technologies, Taiwan
- Amitava Majumdar – Principal Engineer – Xilinx, USA
- TM Mak – Director 2.5D/3D DfT Strategy – GLOBALFOUNDRIES, USA
- “3D Memories: What Is Coming And How Are We Going To Test That?”, Moderator: Françoise von Trapp, Queen of 3D, 3DInCites. Panelists:
- A special session on the status of IEEE P1838 test access standard.
- A special session on ongoing PhD research in 3D-Test.
- Continuous display of table-top demos and posters
- Networking Reception
- and more…
The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc.
Download the 3D Test Workshop Program
REGISTER HERE: Registration is handled through the ITC Test Week Website. If you have already registered for ITC Test Week but not the 3D Test Workshop, you can login using your confirmation code and add the Test Workshop. Follow the instructions on the screen.
