The 2015 3D TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), micro-bumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.
3D TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.
Workshop Program
The workshop program contains the following elements.
- Keynote Addresses: o “New Paradigm Shift in 3-D Design and Testing” by Jeff Rearick – AMD, USA
- 3D Integrated CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications” by K.-T. (Tim) Cheng – UC Santa Barbara, USA
- “Known Good Die – Fantasy Land or Tomorrow Land?” by John Carulli and TM Mak – GLOBALFOUNDRIES, USA
- Four sessions with in total 13 paper presentations.
- Two panel-discussion sessions
- Monolithic 3D: Will It Happen and If So, What Are The Test Challenges and Solutions?
- Test Model Generation for JEDEC 3D Memories: Who Owns the Responsibility?
- Continuous display of table-top demos. Download the detailed program here.
