This industry-wide event is founded upon the co-location of two IEEE conferences which have been at the leading edge of CMOS technology: The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference. An additional third track on 3D Integration is also being included which will emphasize invited talks from world-renowned experts in 3D technology as well as contributed talks from leading research groups and industry.
The Technical Committee for the 3DI Session includes:
Mukta Farooq Paul Franzon
IBM North Carolina State University
Subu Iyer Mitsumasa Koyanagi
IBM Tohoku University
Patrick Leduc Vyshi Suntharalingham
CEA-LETI MIT Lincoln Laboratory
3DI Session Agenda
Thursday October 10th
1:30pm: “3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS“, Toshifumi Irisawa, National Institute of AIST
2:00pm: “3D-Enabled Heterogeneous Integrated Circuits“, C.K. Chen, MIT Lincoln Laboratory
2:30pm: “Three-Dimensional Wafer Stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology“, Pooja Batra, IBM
3:00pm: “3D Hetero-Integration Technology with Backside TSV and Reliability Challenges“, K-W Lee, Tohoku University
For more information and to register, visit the S3S Conference Website
