Materials and Sustainability: Building a Circular Future
Sep 02, 2024 · By Francoise von Trapp · Book Reviews, Resource Library
Latest Posts - Page 4
The X-ray Metrology of TSVs and Wafer Bumps
Being able to look inside an object without opening it up or destroying it, and separating the different features within... ESD in 3D IC Packages
For single die packages, electrostatic discharge (ESD) is well understood, and precautions are taken to minimize the possibility of charge... Technology Options and Their Influence on Routing for Interposer-based Memory Processor Integration
Currently in advanced integration, mainly stacked solutions (Figure 1b) are considered due to their attractive compactness. But if the ASIC... Understanding Heterogeneous 3D Integration
“How is heterogeneous 3D integration defined?” There are certainly different understandings in the microelectronics community regarding the definition of heterogenous...
The Cost of 3D ICs
When 3D integration has been discussed in the past, whether in terms of a true 3D IC stack or an...
Book Review: Vertical 3D Memory Technologies
“From so simple a beginning endless forms most beautiful and most wonderful have been, and are being, evolved.” ~ Charles... Addressing 3D Integration Challenges: Designing Materials for a Complex Landscape
3D integration has created a complex landscape of many different package architectures and integration approaches that have diverse materials needs... Lithography Challenges for 2.5D Interposer Manufacturing
In recent years, 2.5D packaging has quickly gained acceptance as an advanced packaging process, and the first products using this... Glass Substrates for Advanced Packaging
Glass has many properties that make it an ideal substrate for interposers such as: ultra-high resistivity and low electrical loss,... Lithography Process Innovations Part 2: Improving Thermo-mechanical Reliability of TSV Interconnects
In Part 1 of this article series, we noted that despite the potential benefits associated with 3D and interposer-based 2.5D...
Lithography Process Innovations for 2.5/3D Part 1: Alleviating TSV Stress
As traditional semiconductor scaling becomes increasingly complex and cost-prohibitive, transitioning from planar chip packaging architectures to 2.5D/3D stacked die package... Low-Temp, Ultra-Fine-Pitch Cu Interconnections for Manufacturable, Solder-free Assembly
A novel copper interconnection technology is being pioneered by Georgia Tech’s Packaging Research Center (GT-PRC) to achieve manufacturable solder-free assembly at... TSV MEOL Process Flow for Mobile 3D IC Stacking
Moore’s law is approaching physical limitations of CMOS scaling, and three dimensional (3D) integration technologies have been proposed as solutions.... The Internet of Things and Semiconductor Test
Herb Reiter, eda2asic, presented this poster presentation titled “The Internet of Things and Semiconductor Test” at the Test Vision 2020... Market Outlook for Permanent Wafer Bonding
Permanent wafer bonding can be categorized based on bonding with or without an intermediate layer. Intermediate layers can be subcategorized... Electrical Design and Modeling Challenges for 3D Systems Integration
Over the last several years, the buzzword in the electronics industry has been “More than Moore”, referring to the embedding... A Path Finding Based SI Design Methodology for 3D Integration
3D integration is being touted as the next semiconductor revolution by industry. 3D integration involves the use of various interconnects... Path Finding: Who Performs and When?
Microelectronic products all have mechanical, thermal and electrical properties that degrade until the device is permanently damaged. Path finding adds... 