IEEE JETCAS Call for Papers – 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test
Jan 02, 2025 · By Erik Jan Marinissen · Press Releases
Latest Posts - Page 51
EV Group Unveils HVM Photoresist Processing System for Logic and Memory Advanced Packaging Applications
ST. FLORIAN, Austria, February 11, 2014 — EV Group (EVG), supplier of wafer bonding and lithography equipment for the MEMS,... Spirox to Represent Multitest Business for Taiwan and China
In a move to create a strong local presence to enhance sales and support services for its test handler and... Mobility and Internet of Things Drive Requirements for Innovative Sensors
Multitest, a division of LTX-Credence, and designer and manufacturer of final test handlers, contactors and load boards for the semiconductor... Tessera and Samsung Enter into New Patent License Agreements
Tessera Technologies, Inc. and Samsung Electronics Co., Ltd. announced today that Tessera’s subsidiaries Tessera, Inc. and Invensas Corporation each entered... Leaders To Examine EC’s Ambitious Goal At ISS Europe
BERLIN, Germany — January 28, 2014 — At the SEMI Industry Strategy Symposium Europe (ISS Europe 2014) on February 23-25... Meet the Multitest 3D IC Test Experts at the European 3D TSV Summit
Multitest, announces that experts for 3D IC test will present at the European 3D TSV Summit in Grenoble, Jan 20-22,... SSEC Scores Double Tool Win for Thick-Film Removal Processes in Leading Asian Foundry and Major US Chip Manufacturer
Solid State Equipment LLC (SSEC), provider of single-wafer wet processing systems for advanced packaging (including 2.5D and 3D-ICs), MEMS, and... Invensas and Tezzaron Partner to Deliver Commercial 3D IC Products
Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq: TSRA), announced today that it is partnering with Tezzaron... Ziptronix Teams with Tezzaron and Novati Technologies to Accelerate 3D IC Development
Ziptronix Inc., provider of patented, low-temperature direct bonding technology for 3D integration, announced an agreement with Tezzaron Semiconductor Corporation and... CEA-Leti Signs Agreement with Qualcomm To Assess Sequential 3D Technology
CEA-Leti announced an agreement with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to assess the feasibility and the value... EV Group Completes Next Expansion Phase of Corporate Headquarters
ST. FLORIAN, Austria, December 05, 2013 — EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for... Successful 2.5D Test Vehicle Project Launched by GLOBALFOUNDRIES, Open-Silicon and Amkor Technology
GLOBALFOUNDRIES has unveiled details of a 2.5D test vehicle project that demonstrates the value of its open and collaborative approach... Rudolph Wins Multiple Orders for AWX FSI Unpatterned Wafer Inspection Tools in Back-End and Advanced Packaging Applications
Rudolph Technologies, Inc. announced that it has won orders for its AWX™ FSI unpatterned wafer inspection system at both a... SUSS MicroTec Brings 3D IC Laser Debonding to Fraunhofer IZM
SUSS MicroTec announced the installation of its ELP300 excimer laser stepper to support next-generation advanced packaging and 3D IC laser... 3D Memory Using Conductive Lines for Vertical Interconnects
The push for size reduction is reaching the segment of vertical interconnects. Current technology has a lower limit of approximately... NANIUM Extends eWLB to Achieve Higher Reliability
NANIUM S.A. has introduced an improved dielectric material and process solution for its fan-out wafer-level packaging (FOWLP) technology, embedded wafer-level... Triton Microtechnologies Receives Funding to Ramp Glass Interposer Manufacturing for 3D and 2.5D Semiconductor Packaging
Start-up Triton Microtechnologies, a designer and manufacturer of ultra-thin glass interposer technology that enables advanced semiconductor-packaging solutions, has met six-month... Dow Introduces SOLDERON Tin-Silver Plating Chemistry for Lead-Free Bumping
The company’s next-generation SnAg offers industry-leading plating rates and process flexibility for flip chip packages and interconnects. Dow Electronic Materials... Delft University of Technology and imec Introduce 3D-COSTAR to Optimize Test Flows of 3D Stacked Integrated Circuits
Delft University of Technology (TU Delft) and nanoelectronics research center imec, introduced 3D-COSTAR, a new test flow cost modeling tool... 