IFTLE 614: What’s in Store for Intel’s Future? Update on NAPMP Proposers Day
Dec 11, 2024 · By Phil Garrou · Blogs, Packaging IFTLE
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IFTLE 447: Micron and Rambus Readying HBM2 3D Stacked Memory Products
If we look back, almost a decade ago, 3D stacked memory was all the rage, and the leader in stacked...
IFTLE 446: 2.5/3D Inspection; Embedded Chip Tech; Wide Bandgap Semi Roadmap
Let’s look at a few more presentations from the SEMI 3D & Systems Summit which was held in late January...
IFTLE 445: Hybrid Bonding at Xperi, GLOBALFOUNDRIES and Besi
The expansion of hybrid bonding as a process for high-density packaging was the topic of some presentations presented at the...
IFTLE 444: Chip on Interposer on Substrate vs High Density Chips-Last Package Cost Modeling
This year’s SEMI 3D & Systems Summit was held in late January in Dresden. In the next few blogs, we...
IFTLE 443: Controlling Warpage and Placement Error for FOWLP
In the Jan/Feb issue of ChipScale Review, there were two interesting articles on fan-out wafer-level packaging (FO-WLP) entitled “Eliminating Warpage...
IFTLE 442: Intel Joins CHIPS Alliance; 3D Stack Testing Standardized
Everyone by now should know that Intel has been a lead member of the DARPA “CHIPS” program fostering and developing...
IFTLE 441: Will TSMC Ever Put a Chip or Packaging Facility in the USA?
While we are all conjuring visions of what advanced packaging and in fact transistors themselves will look like in the...
IFTLE 440: Copper Pillar Bump Development for 7nm Node Devices
In the latest issue of IMAPS “Advancing Microelectronics” magazine (Nov/Dec 2019) Lei Fu and his colleagues at AMD published an...
IFTLE 439: imec’s Flip Chip on FOWLP… a Closer Look
3D InCites presented the 2019 process of the year award to Eric Beyne and Arnita Podpod of IMEC for their...
IFTLE 438: Reliability Test For 0.3mm WLCSP; Copper RDL Trace Requirements
This week we continue our look presentations from SEMICON Europa’s Advanced Packaging Conference. Intel’s Reliability Test Beth Keser’s group at...
IFTLE 437: Packaging Trends for Artificial Intelligence
As it has in recent years, SEMICON Europa 2019 featured a dedicated Advanced Packaging Conference. In this and my next...
IFTLE 436: Fluxless µBumping; Latest on Stacking Technologies
The November Issue of Chip Scale Review contains some interesting advanced packaging information that is worthy of sharing in IFTLE:...
IFTLE 435: The Heterogeneous Integration Roadmap (HIR)
Before we start this week’s blog, let me take the opportunity to wish all IFTLE readers a Merry Christmas and...
IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller
There are several different fan-out wafer-level packaging (FOWLP) technologies that are currently in high-volume production. The traditional fan-out (FO) technology...
IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet Standardization
In 2017, AMD used chiplets in their “Zen 2” architecture to develop the Epyc server processor “Naples” (Figure 1). AMD...IFTLE 432: Ferric and TSMC Partner on Voltage Regulators; High TC Die Attach for TIM?
The IMAPS International Symposium took place this year in Boston. Let’s take a look at a few of the more...
IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration
Samsung reports that they have seen increasing interest in multi-die integration (what they call MDI) for markets such as artificial...
IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key!
Beyond HPC High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s...
IFTLE 429: Samsung 12-layer memory with 3D-TSV; SHIP Winners
Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically...
