The Role of Chiplets in Redefining Semiconductor Design
Dec 05, 2024 · By Cadence · 3D In-Depth, Design
Design View all
Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D
Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices. These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or...
A Focus on Chiplet Verification
Chiplets have become a strategic asset for designers who are implementing them in all sorts of applications. Until now, chiplet verification until now has been overlooked. I discussed this phenomenon with Dave Kelf, CEO of Breker Verification Systems, an ESD Alliance member company and provider of verification solutions that leverage...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 27
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Suppliers offer solutions to TSV formation challenges
As part of the 3D tracks at both this year’s International Wafer Level Packaging Conference, held October 27-30 in...
Discussion Summary: Overcoming weaknesses in dry processes for TSV metallization
This week’s online forum with Alchimer’s executive team, Steve Lerner, CEO; Kathy Cook, Director...Terepac begins pilot production of printed silicon ICs
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Taking the “pick” out of pick-and-place
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Bringing Transparency to 3D Integrated Structures – Olympus Confocal IR Microscopy
Metrology is consistently one of the more challenging areas in the semiconductor field. Whether it’s the monitoring of ultra-small...
Inside CEA-Leti’s 3D Toolbox
Grenoble-based research institute CEA-Leti’s progress is fueled by a single mission: create innovation and transfer it to industry. The goal...SUSS MicroTec workshop zeroes in on wafer thinning and handling issues
Last year, it was all about through silicon vias (TSVs), this year, it’s all about everything else needed to...
IMEC and SUSS MicroTec to collaborate on wafer bonding for 3D integration
SUSS MicroTec and IMEC have entered a joint development program to develop permanent bonding, temporary bonding...Trends and challenges for thin wafer processing
Processes addressing the handling of ultra-thin wafers have been a hot topic ever since it became clear that they are...3d is hot at SEMICON West
Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's...
