Unlocking the Mystery of X-Ray Imaging for Electronics and Semiconductor Inspection
Apr 23, 2025 · By Excillum · 3D In-Depth, Test and Inspection
Design View all
Multi Physics Analysis of 3D Integrated Circuits
3D integration is becoming a valuable alternative to the ongoing, yet challenging, transistor scaling known as Moore’s Law. This is especially true for semiconductor products that are becoming limited by single die designs (e.g., in terms of form factor, size, and technology node). Homogenous 2.5D-IC approaches help bring about the...
Taking 3D IC Heterogeneous Integration Mainstream
By Tony Mastroianni and Todd Burkholder, Siemens DIS Over the last several years, chiplet-based heterogeneous package integration has emerged as a promising alternative to traditional monolithic package solutions; the so-called homogenous SoC design. 3D IC heterogeneous integration is a system approach, wherein what typically would be implemented as an SoC...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 26
EV Group Installs its Wafer Cleaning System for Compound Semiconductor Research at the University of Tokyo
EVG System Enables Void-free Wafer Bonding of III-V Compound Semiconductor Materials on Silicon Wafers with High-quality Surface Preparation TOKYO, JAPAN,...Progress is Progress in the Medical Device World
This was my second year attending the Medical Electronics Symposium, and I’m not sure what I was expecting, but when...The Inside Scoop from GSA’s EDA 3D/TSV Interest Group
Guest contributor, Herb Reiter, reports from the Sept 13 meeting of the GSA’s 3D/TSV EDA Interest Group, where 55 attendees,...Prior Predictions
Every once in a while, it’s helpful to step back and get a broad view of what’s going on in...SUSS MicroTec Appoints New VP R&D
SUSS MicroTec has appointed Dr Rainer Knippelmeyer as VP R&D and CTO. In this function Rainer Knippelmeyer will oversee research...SEMATECH Completes Fully-integrated 300mm Line for Via-mid 3D ICs
In an ongoing effort to drive 3D IC integration, SEMATECH’s 3D Interconnect program has completed its 300mm 3D IC pilot...Lowering integration risks for 3D TSV products
A critical challenge for fabricating 3D products is the integration of the dies with through-silicon vias (TSVs) into functioning and...SEMATECH, SIA and SRC Team to Establish New Collaborative Program for Enabling 3D ICs
SEMATECH, the Semiconductor Industry Association (SIA), and Semiconductor Research Corporation (SRC) announced today they have established a new 3D Enablement...SPTS Opens New San Jose Facility At Silicon Valley Research Center
SPP Process Technology Systems (SPTS) announced the opening of its new facility in San Jose, CA, serving as the home...SEMICON West: Success for 3D –focused Companies
Is it mere co-incidence that companies who have invested in 3D technologies seem to have escaped the effects of the...
Extending Legacy Technologies into the 3D Space
While TSVs technologies make their way out of R&D on to the manufacturing floor, improvements and developments in non-TSV 3D...EV Group Capitalizes MEMS Market Leadership, Further Diversifies Business with 3D IC and LED Manufacturing Technology Advances
Company to share key developments and highlights at SEMICON West
Alchimer Introduces Via Fill Technology
Alchimer S.A. has announced a groundbreaking advanced technology for filling narrow, high-aspect-ratio TSVs while significantly reducing...CMP/CMC/MOSIS partner to introduce a 3D-IC process
CMP/CMC/MOSIS announced a Grenoble-France based partnership for a 3D-IC multi-project wafer (MPW) service based on Tezzaron’s SuperContact technology and...
ECTC 2010 Panel Examines the Medical Device Market
Keith Cooper, Technology and Development, SET North America reports from ECTC 2010's Medical Device Market Panel, offering a view beyond...CEA-Leti and Docea Power to Combine Expertise on 3D Integration, Thermal and Low-power Design
French research insitute, CEA-Leti and Docea Power, developers of software for power and thermal analysis at the architectural level,...
CEA-Leti and SPTS to Collaborate On Next-Generation TSV Development
CEA-Leti and SPP Process Technology Systems (SPTS) have agreed to develop advanced 300mm through-silicon via (TSV) 3D-IC processes at CEA-Leti’s...EV Group Introduces New EVG610 Mask and Bond Aligner Optimized for Greater Cost and Process Flexibility
New System Provides World-class Alignment Technology at an Affordable Cost
