The Role of Chiplets in Redefining Semiconductor Design
Dec 05, 2024 · By Cadence · 3D In-Depth, Design
Design View all
Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D
Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices. These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or...
A Focus on Chiplet Verification
Chiplets have become a strategic asset for designers who are implementing them in all sorts of applications. Until now, chiplet verification until now has been overlooked. I discussed this phenomenon with Dave Kelf, CEO of Breker Verification Systems, an ESD Alliance member company and provider of verification solutions that leverage...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 2
Heterogeneous IC Packaging: Building an Infrastructure
Heterogeneous IC packaging is here. It is already in production, and increasingly more customers are developing and qualifying their products...
Excitement Over Chiplets: Not for Everyone and Not Trivial for Test
Live from “Silicon Desert”: The news is all about huge spending by TSMC and Intel. Investment in advanced packaging (2.3/2.5/3D...
Digital and Physical: Thermal Twins for Developing Thermal Management Solutions
As we all know, finding thermal management solutions is becoming an increasingly critical but also an ever more challenging issue...
Updates in Test Connectivity System (TCS) from TestConX
The annual TestConX conference (www.testconx.org) was held March 5-8, 2023, in Mesa, Arizona. It offered a one-of-a-kind, one-stop shop for...
Wafer Bonding and NanoCleave: The New Lithography Scaling
NanoCleave enables Laser Debonding on Silicon with Nanometer Precision In semiconductor manufacturing, 3D integration – the manufacturing, vertical assembly, and...
Sustainability 101: What Good Are Awards?
Awards and rewards can motivate behavior. An obvious example is online gaming, where players earn stars, points, or access to...
Interconnect Reliability: From the Chip to the System
Interconnect reliability is critical to the reliability of semiconductor packaging and electronic systems. If we look at the life cycle...
Building Chiplet Systems: Models
There is a general agreement that chiplet systems are the next step in the evolution of designing dense, complicated, and...
SiC MOSFET Challenges, Demand and Industrialization of Test & Burn-in
The coming-of-age and breakthroughs offered by silicon carbide (SiC) MOSFETs, as well as demand that is outstripping supply are rapidly...
Forging a New Future for 3D IC Design and Architecture
The semiconductor industry’s ability to coax more and more performance out of a chip has produced the most significant innovations...
Update on the UCIe™ from ITC 2022
In 1965 Gordon Moore proclaimed that there would be a “’Day of Reckoning’ when it may prove to be more...
Building a Dense 3D-IC System: Power Challenges
Recently, there has been a very healthy discussion on whether Moore’s law is still valid. While the arguments fly from...
Chiplet Designs and Heterogeneous Integration Packaging
System-on-Chip (SoC) integrates ICs (by reducing the feature size) with different functions such as central processing unit (CPU ), graphic...
Materials Science Solutions for Electronics Sustainability
This summer, the temperature reached 111°F in Silicon Valley, where I live. This historical record unmistakably brought home the “inconvenient...
Thermal Analysis Techniques to Improve High Density Semiconductor System Performance
Thermal problems in semiconductor electronic systems often go unnoticed and cause failures. Although thermal problems can be understood and avoided...
Maskless Lithography Addresses Shift Toward Heterogeneous Integration and 3D Packaging
Moving from 2D scaling to heterogeneous integration and 3D packaging is ever-more critical to improving semiconductor device performance. In recent...
Development of Innovative Advanced Packaging Materials for System in Package
Advanced packaging has continued to evolve with various interconnect technologies on their way towards heterogeneous integration. Different assembly processes are...
Understanding Wafer Applications in Surface Metrology
This detailed blog covers how wafers are manufactured and processed, what makes a perfect wafer, and which surface metrology approaches...
Contributing to a Greener Semiconductor Industry
Recently we read an interesting article here on 3D InCites about the role secondary markets play in contributing to a...
