The Role of Chiplets in Redefining Semiconductor Design
Dec 05, 2024 · By Cadence · 3D In-Depth, Design
Design View all
Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D
Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices. These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or...
A Focus on Chiplet Verification
Chiplets have become a strategic asset for designers who are implementing them in all sorts of applications. Until now, chiplet verification until now has been overlooked. I discussed this phenomenon with Dave Kelf, CEO of Breker Verification Systems, an ESD Alliance member company and provider of verification solutions that leverage...
Devices View all
How AiP Technology Helps Enable 5G and More
For 5G smartphones and other millimeter-wave (mmWave) applications, antenna integration, either through antenna-in-package (AiP) or antenna-on-package (AoP) technologies, simplifies the challenges associated with designing products that operate at these high frequencies. A variety of AiP/AoP design methodologies provide the required form, fit, and function for these applications and can include...
System-on-Chip Disintegration is Underway
We have known for some time that with scaling coming to an end the industry would need to find another way to continue moving forward. One of the options is known as SoC disintegration, which is when a system-on-chip (SoC) is disintegrated into its functional parts and then connect these...
Latest Posts - Page 11
Lasertec: BGM300
The BGM300 was designed to enable quick and accurate measurement of Through Si Via (TSV) depths, Si wafer thickness, and... Fogale: TMAP DUAL 3D 300 A
The TMAP DUAL 3D 300 A is a unique metrology and inspection tool available to the semiconductor industry capable of... NORDSON Dage: XM8000 Wafer X-ray Metrology Platform
Fully automatic, in-line X-ray metrology platform for the measurement and defect capture of both optically hidden and visible features in...
ECTC 2014: A Preview of 2.5D and 3D Activities
Each year, the agenda of Electronic Components Technologies Conference (ECTC), an international conference sponsored by the IEEE Components, Packaging, and Manufacturing...
An Open Letter to Chip and System-level Designers Regarding 3D Integration
Dear Chip and System-level Designers, Allow me to introduce myself. My name is Françoise von Trapp, and I am known...
2013 ITRS Roadmap Calls for 3D Power Scaling; Monolithic 3D Gains Traction
At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS), which has traditionally... Rudolph Technologies: JetStep S Series Lithography System
As advanced packaging facilities transition their manufacturing from round wafers to square panels, the JetStep S Series Lithography System is...
ASE and Inotera Memories to Offer Novel 2.5D Manufacturing Solutions
Last week, ASE and Inotera Memories announced they had entered into a joint development project (JDP) intended to both strengthen...
Cascade Microtech: In the imec 3D Test Lab
My visit to imec to meet with the Cascade Micorotech and imec 3D Test collaboration team included a tour of...
Cascade Microtech Breaks Through the Barriers of 3D Test
For quite some time, the lack of cost-effective test solutions for 2.5D interposers and 3D stacked ICs (3D SICs) has...
3D Workshop Panel Discussion Focuses on 3D Standards and EDA Tool Readiness
Are slow standardization and CAD-tool development hindering the progress of 3D IC design and integration? This was the topic of discussion...
SUSS MicroTec Launches Mask Aligner MA200 Gen3
Garching, April 2, 2014 – SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and...
3D Integration Workshop Faces Reliability Challenges Head On
The Friday 3D Integration Workshop at DATE 2014 once again found me among friends, as an intimate group of about...
Fogale Nanotech: Building The Swiss Army Knife of 3D IC Metrology and Inspection
In the world of 3D ICs, where features are becoming finer and submicron accuracy and precision is more important than...
A Solder Bump Expert’s Take on the Expanding World of Advanced Packaging
An interesting take-away from the keynote talk delivered by Brandon Prior, Prismark Partners, at this year’s IMAPS International Device Packaging...
Latest Developments in Cleans for TSVs and Cu Bumps
At IMAPS DPC 2014, which took place March 11-13, 2014, in Fountain Hills, AZ, there were several presentations focused on...
Making Progress with 3D IC Design and Test
Thank you, Ann Steffora Mutschler (Semiconductor Engineering) for getting to the bottom of the difference of EDA tools for 2.5D...
TCI for Wireless Chip Stacking; Progress for Monolithic 3D
Every once in a while, it’s important to remember that through silicon vias (TSVs) might not be the only game...
Progress Reports for 3D IC Thermal Management and Test
In Jan Vardaman’s recent readiness report card issued at 3D ASIP in December, 3D IC thermal management issues scored and...
