FO-PLP packging substrate/AT&S

Fan-Out packages have recently been introduced in high-end applications with miniaturization, cost reduction and shorter time to market for electronic products drives the need for heterogeneous integration in a single package module. PCB-based technologies which combined with substrate, embedding and assembly technologies can offer integration as a single package. AT&S will introduce relevant market data on miniaturization, modularization and system-level electronics integration including newly proposed fan-out concepts on panel level. As part of these, we have been developing the multiple dies embedding FO-PLP substrates with symmetric and asymmetric build as Chip first and RDL on carrier as Chip Last, and .especially we have not only demonstrated the PCB process ability with fine structuring(L/S ≤5/5um, Via ≤30um, ±3um assemble accuracy..) and embedding PTCQ(Packaging Test Chip version Q) active dies from imec, but also have checked a good performance from package testing imec.