In response to the rising costs of advanced nodes and the slowdown of Moore’s Law, major vendors – AMD, Intel, Apple, and Samsung – are making the shift towards chiplet-based systems using 3D technologies, which create novel system partitioning through modular and scalable architectures. These solutions optimize bandwidth with respect to power consumption, contributing to the current energy-sober trend. The very short interconnects in chiplets also reduce data transfer latency. However, the unprecedented growth of artificial intelligence (AI) applications creates new and significant energy demands. Consequently, advanced packaging ecosystems are needed to deliver faster and more cost-effective systems with ever-greater functionality, performance, and power efficiency.
The Chiplet Market
By 2028, chiplets are projected to be almost ubiquitous in high-end data centers housing generative AI and computational processors (Figure 1), and needs are emerging in the consumer and automotive markets. For example, 3D integrations are already included in some high-end consumer products such as imagers (from Sony or STMicroelectronics), where they optimize the power, performance, area, and cost (PPAC) trade-off.
To produce 3D technologies and packaging, major semiconductor companies currently depend on a fully integrated ecosystem with constraints on wafer sources. Some (e.g. Intel) have developed in-house technology, whereas others use proprietary 3D toolboxes and technologies from leading foundries such as TSMC, based on specific ecosystems and wafer sources.
If the chiplet market is to expand, companies must be able to process any wafer from any foundry.
CEA-Leti, a pioneering RTO in FD-SOI technology with 20 years of experience in the lab-to-fab ecosystem, has taken up this challenge to help the chiplet market. Thanks to interactions with the French public nanoelectronics research institute (IRT Nanoelec) – 22 partners from academic research and industry – and with leading equipment manufacturers, system integrators, and EDA vendors, CEA-Leti has access to the latest heterogeneous 3D technologies, including materials and wafers from several foundries (e.g. SET, EV Group, and Applied Materials).
Network-on-Chip and Advanced Architecture Optimization
The chiplet-on-interposer approach integrates chips with diverse functionalities on a unified silicon platform to support analog, low-power digital, and enhance 3D communications, particularly in network-on-chip architectures. Back in 2019, CEA-Leti initiated this concept by demonstrating 28 nm FD-SOI chiplets stacked on an active 65-nm interposer [1].
Die-to-wafer (DTW) hybrid bonding (feature image above) combining copper/oxide interfaces, can produce interconnect pitches <5 µm (traditional copper pillars measure >20 µm). Using DTW, CEA-Leti has produced chips with pitches <2 µm, creating new architecture possibilities for very heterogeneous systems. Further optimizations to increase yield and reduce costs are currently being tackled.
Standard hybrid bonding (HB) temperatures (400 °C) are too high to be compatible with 3D integration of memory functions (maximum 200-300 °C) and active devices – quantum bit and some photonic applications – (150 °C or less). In response, CEA-Leti has developed a low-temperature process flow and a new plating process, achieving bonding at temperatures as low as 200 °C thanks to copper microstructure optimization [3].
When combined with through-silicon vias (TSVs), WTW becomes the cornerstone of 3D integration, ensuring efficient signal transfer and power distribution in vertically stacked layers. CEA-Leti has successfully developed a 3-layer test vehicle (TV) with hybrid Cu-Cu bonding interfaces and high-density TSVs [4], ready for application in functional 3D advanced CMOS image sensors (Figure 2).
Advances in Photonics and Co-Packaged Optics
Next-generation optical transceiver modules have been created by combining photonics integrated circuits (PIC) with TSVs, advanced flip-chip, or fan-out wafer-level packaging (e.g. by Intel/Ayar Labs and Broadcom). This co-packaged optics approach combines micro transceivers with host chips (e.g., Ethernet switches, CPUs, FPGAs), reduces radiofrequency (RF) path length, and improves data transfer rates and connectivity. This approach is an ideal playground for advanced heterogeneous integration, with its requirements for enhanced electronic/photonics cross-talk, especially in optical communication and networks and for AI/HPC computing systems.
CEA-Leti anticipated the photonics trend, and its specific needs, as demonstrated by the recent production of a successful TSV middle process in a silicon photonic flow for a functional Lidar application within the Tinker project [5]. The most recent development concerns the ongoing fabrication of the first Optical Network on Chip based on a photonic interposer hosting four many core chiplets and six transceivers. This approach may overpass the latency wall and bandwidth for massively parallel computing applications [6] (Figure 3)
This last prototype involves the post-processing at Leti of the last metal layers, passivation deposits, and micro bumping of Fully Depleted SOI 300 mm wafers coming from STMicroelectronics for the Chiplets and Transceivers dies. In this particular case, it implies two different foundry multi-project wafers run with their own lithography mapping showing the ability of Leti 3D technologies to be applied to outsourced wafers.
Open 3D Process for the Chiplet Market
In response to the paradigm shift in the semiconductor industry to expand the chiplet market, CEA-Leti joined the European multi-hub Test and Experimentation Facility PREVAIL [7], with Imec, the Fraunhofer-Gesellschaft, and VTT, to target hardware innovations for edge AI applications, specifically focusing on small-pitch copper HB and TSVs.
Within the European Chip Act, the European Commission has accepted CEA-Leti’s FAMES pilot line. These new 10-7 nm FD-SOI technologies involve extensive 3D integration at small-pitch, and set ambitious architectural innovation targets for 2028 in terms of computing and RF communications, with significant performance gains expected from heterogeneous systems combining silicon technologies, III-V technologies, and other materials. The FAMES line will promote interactions between users and stakeholders in the electronic value chain, including researchers, SMEs, start-ups, and large industrial groups.
References
This work was partly supported by the French National program “IRT Nanoelec”, ANR-10-AIRT-05, and by the European Union’s H2020 funding (grant No. 958472 (TINKER)).
[1] P. Coudrain, et al., “Active interposer technology for chiplet-based advanced 3D system architectures,” IEEE 69th Electronic Components and Technology Conference (ECTC), May 2019, pp. 569‑578
[2] M. Maubert et al., “Copper Microstructure Optimization for Fine Pitch Low-Temperature Cu/SiO2 Hybrid Bonding,” IEEE 74th ECTC, May 2024, Denver, USA
[3] S. Nicolas, et al., “3-layer fine pitch Cu-Cu hybrid bonding demonstrator with high-density TSV for advanced CMOS image sensor applications,” IEEE 74th ECTC, May 2024, Denver, USA
[4] T. Mourier et al., “Advanced 3D integration TSV and flip chip technologies evaluation for the packaging of a mobile LiDAR 256 channels beam steering device designed for autonomous driving application,” IEEE 73rd Electronic Components and Technology Conference (ECTC), 2023
[5] D. Saint-Patrice et al., “Process Integration of Photonic Interposer for Chiplet-based 3D Systems,” IEEE 73rd Electronic Components and Technology Conference (ECTC), 2023,
