Security threats are a hot topic of discussion today as they can have a profound impact on the electronic infrastructure and devices that are the backbone of our global economies. It is also clear that these threats can also be introduced during the design of the very devices that we rely on in our daily lives.
Chiplet-based design is growing rapidly and the industry is recognizing that security measures must be taken during the design flow to ensure that security threats are not introduced — whether inadvertently or with malicious intent. These threats generally fall into one of two categories. The first is the unintentional hardware threats (circuitry) that may be a byproduct of automated circuit design technologies used to create complex chips. The second category includes hardware, such as trojans, that are maliciously and deliberately added to the design and can lie hidden within the design until triggered by specific signals or patterns.
Chiplets can come from many different sources and simultaneously the industry demand for new chiplet-based designs is accelerating. The industry needs to come to grips with the fact that the threats are real and that bringing security to the design flow is critical. Achieving this will require industry input, collaboration, and consensus on supporting best practices and technologies for combatting these security threats.
The ESD Alliance, a SEMI Technology Community, and ESD Alliance member company, Silicon Assurance, are hosting an industry panel and discussion webinar on Thursday, March 14, from 9 a.m. – 10 a.m. PST. The panel discussion will be moderated by Raj Gautam Dutta, CEO and co-founder of Silicon Assurance, a company focused on addressing trust and security assurance in the chip design flow.
Panelists come from a broad cross-section of the chip design industry and will discuss the threats that can occur during the various stages of the design flow and during assembly and test. They will also consider the latest advancements and different approaches that can be employed to safeguard the future of chiplet-based design.
The panelist includes Swarup Bhunia, Semmoto Endowed Professor and Director of the Warren B. Nelms Institute; Steve Carlson, Director/Solutions Architect, Aerospace and Defense Solutions at Cadence Design Systems; John Hallman, Digital Verification Technology Solutions Manager for Siemens EDA; Serge Leef, Head of Secure Microelectronics at Microsoft; Salman Nasir, Senior Technical Program Manager from Battelle; and Ming Zhang, Vice President of R&D Acceleration at PDF Solutions.
Please join us for a better understanding of the magnitude of the potential threats and how the industry can come together to address them.
Registration for the virtual webinar Chiplet Security—Current and Future is free. Registration details can be found on the ESD Alliance website.
