A critical challenge for fabricating 3D products is the integration of the dies with through-silicon vias (TSVs) into functioning and reliable 3D stacks. As a way to assess and overcome the risks, imec has created the SmartSamples platform. SmartSamples allow validating 3D stacks before the actual product design, avoiding costly re-spins and additional expenses. They are IC emulators, prototype 3D IC packages enhanced with sensors that collect data on temperature, stress, and performance of the electrical circuits in the 3D package.
Integration and stacking challenges
Over the past few years, the industry has worked hard to make 3D technology reality. Several flavors have been developed, each with its own characteristics, costs, manufacturing challenges, and application sweet spots. An example is the 3D-SIC technology that was developed by imec and its partners. This technology has the distinct advantage that it allows reusing existing IC foundry infrastructure to fabricate TSVs after the front-end-of-line (FEOL) processing and before back-end-of-line (BEOL) processing.
Through this and other work, the risks and costs related to TSV processing are now known. But the integration of dies into a stack and package still remains a critical challenge. Take for example the hot spots that could appear if the power dissipation is not carefully managed across the tiers in a 3D stack. Hot spots are small areas with high power dissipation leading to localized temperature increases, caused by the reduced thermal spreading in the thinned die and by poorly conductive adhesives.
To study the thermal impact of hot spot size and power density on 3D stack design, imec started doing thermal finite element simulations, calibrated with a test structure embedded in the 3D stack. This consists of heaters (metal resistors) integrated with thermal sensors (diodes). The heaters are located in the metal 2 layer of the BEOL in the top tier of the 3D chip-stack, as well as in a 2D reference die.
The results of these tests indicate that power dissipation approximately has a three times higher maximum temperature increase in 3D stacks than in a 2D IC. There’s also a three times higher thermal gradient for hot spots with sizes ranging from 50µm to 100µm, requiring thermal-aware floor-planning to avoid thermal problems in the stack.
SmartSamples to assess and lower the integration risks
Today, IC manufacturers mainly address thermal and thermo-mechanical challenges during the package design. In this phase, the design and material properties of the package are iteratively optimized until all the specifications are met.
But this iterative approach comes with long cycle times and is expensive. The main reason is the increasing complexity of package design and manufacturing, leading to even more issues of thermo-mechanical stress.
As a solution, imec has developed the SmartSamples platform, which allows validating the manufacturability and the integration scheme of the envisioned 3D stack before the actual product design. In doing so, costly re-spins and additional expenses can be avoided.
SmartSamples are IC emulators enhanced with sensors, extracting data on temperature, stress and performance of electrical circuits in the package. The information from the SmartSamples is used in two ways:
- To optimize the yield and reliability of the stack by optimizing the integration scheme and process (die-to-die, die-to-wafer), microbump geometries, underfill materials and packaging options. We use the SmartSamples, for example, to look at the stresses that are induced by the TSV processing with various liner and plating technologies.
- To set design rules and models for steering the actual product design. The figure below shows a thermal compact model. It enables a quick evaluation of thermal behavior in a 3D chip-stack, calibrated against Si to predict the temperature gradients in prototype and product chips. During design, many degrees of freedom are available to manage these stresses (e.g. by layout, by introducing thermal bumps, stack floorplanning, etc.). Then, after successful verification of thermo-mechanical/thermal stresses, the tiers of the stack can be taped out with a higher confidence of using a reliable packaging solution.
Figure 3D smartsamples: Snapshot of thermal compact model calibrated using SmartSamples. On the left are the input parameters, centrally the power maps on the 3 tiers, and on the right the temperature profiles of the 3 tiers in the stack.
Today, we can build these smart samples significantly faster than actual prototypes. This makes it possible to do a quick evaluation of electrical, thermal and thermo-mechanical issues, even before the product design. To do so, we have put an extended database of test structures in place, together with scripts to calibrate the design rules and models. Importantly, we leverage our 300mm platform for generating these samples on short notice.
This article first appeared in imec’s August 19 newsletter, and was republished with permission from imec, www.imec.be, August 2010.
