At MIT Lincoln Labs (MITLL), R&D processes developing 3D chips using silicon-on-insulator (SOI) wafers is the sole focus. As Phil Garrou, Ph.D. reported in his 3D status update at the pre-conference symposium during last month’s RTI 3D Architectures for Semiconductor Integration, DARPA chips are done on this line, and they’re turning out “active product”, as long as it can be done in SOI.
During the conference itself, Craig Keast, of Lincoln Labs, provided more detail on the SOI-based wafer-level 3D IC integration, explaining the advantages of SOI versus bulk CMOS as follows: The electrically active portion of an IC wafer is <1% of its total thickness. The buried oxide layer on SOI provides an ideal etch stop for wafer thinning prior to 3D integration. Full oxide isolation between transistors allows direct 3D via formation without the added complexity of a via isolation layer. SOI’s enhanced low-power operation (compared to bulk CMOS) reduces circuit stack heat load.
Keast described a three tiered wafer-to-wafer process flow using a face-to-face direct oxide bond, and tungsten-filled wafers. For the carrier wafer, he said either SOI or bulk silicon can be used. This process flow relies on three distinct enabling technologies, noted Keast. The first is a precision 200mm wafer aligner-bonder designed at MITLL, and assembled and installed in the class -10 microelectronics lab. This tool reportedly enables technology for aggressive 3D via pitch, and has demonstrated a <0.5µm 3-σ overlay. The second is a low-temperature oxide-to-oxide bond that delivers a high-strength bond for Si fab, chip sawing, wire bonding, and thermal cycling. Furthermore, the oxide-oxide bond allows for standard IC processing to complete 3D integration because it replaces the epoxy adhesive. The last enabling technology discussed by Keast was a concentric 3D via with a CVD tungsten fill process for the electrical connection. The concentric 3D vias allow for much higher density, noted Keast.
Initial technology demonstrations at MITLL are centered around advanced focal plane architectures, because as Keast pointed out, for them this is the “low hanging fruit.” The organization is largely funded by DARPA to explore new 3D circuit applications, and they have established a Multiproject Run model to allow researches from government, academic, and industry design groups to explore 3D design approaches. Primarily, they’re looking at FPGAs, dense memory, memory on processor, mixed signal systems, and mixed material systems.
From the perspective of MIT-LL’s approach, Keast observed that 3D integration “isn’t cheap”, and application /benefit gain needs to justify the cost. He cited issues still to be ironed out as alignment, compound yield loss, and heat dissipation in the stack. However, he noted the potential yet to be realized, which could very well revolutionize the design architecture of future circuits and systems.
