And what are we going to do about it in 2015…?
A moment ago I finished reading my predictions for 2014. I wrote them on January 11, 2014, almost exactly one year ago. After convincing myself that I was roughly on target, I am going to stick my neck out again, and, hopefully, give you some food for thought.
I hope you can agree with me that my previous predictions, emphasizing good prospects for 2.5D ICs and 3D memory cubes in 2014, were roughly on target. Therefor please lend some credibility to my predictions for 2015 and help my missionary work for strengthening the 2.5/3D EcoSystem further.
First things first! As 2014 demonstrated, “2.5D” technology (stacking dies side-by-side on an interposer) is not just a compromise or an interim step towards the “real 3D-IC” technology (vertical stacking of dies). It’s a very viable alternative to vertical stacking and for many applications actually better suited than 3D. That’s why many experts want the initially coined “2.5D-ICs” term buried and use instead “Interposer-based ICs”. As you can see above, the title of this blog is already industry compliant.
Looking back at 2014 and recalling my impressions from recent 3D conferences, I am, like many of you, wondering why especially smaller and medium size companies are still not investing in one or both of these technologies. Compared to PCB-based multi-die implementations and PoP or SiP solutions, interposer-based designs offer much better performance/power ratios and often smaller form-factors. Clearly, for very high volume applications, even smaller firms should consider 3D IC solutions.
This scenario leads me to my first prediction for 2015: More EDUCATION and TRAINING
- 2015 will bring significantly more educational efforts for system- and IC designers as well as packaging and reliability engineers to clearly convey the benefits interposers and vertically stacked dies can offer for these companies’ specific applications. Demonstrating the readiness of both alternatives is of course also important to really motivate these technical experts to change paradigm.
- All the new technologies I have been promoting during my ~40 years in semiconductors have initially been more costly – from a component level – and should not be compared with proven and many times cost-reduced components. New components’ unit cost always declined rapidly, as volume production starts. Higher level management also needs to be informed about potential SYSTEM-level savings. In addition, the impact of higher performance, lower power dissipation, smaller form-factor and other benefits will allow the supplier to charge more. The achievable sales price and the resulting profit margin have to be analyzed, before concluding “too costly”. Also, the ability to re-use these die-level building blocks, the savings on development time and cost, due to their modularity, also compares favorably with a single-die, SoC implementation.
- The many 3D-focused conferences in 2015 will contribute to this educational effort. EDA vendors, 3D Design Services and I have concrete plans to contribute to Education & Training.
My second prediction for 2015 simply is: Better COOPERATION across the EcoSystem
- In my role as Director, 3D-IC Programs at Si2 (Silicon Integration Initiative in Austin) I really enjoy the high level of interest large corporations (Intel, IBM, Qualcomm, AMD and others) show for interposer and 3D-IC technology in our regular 3D Technical Advisory Board (Open 3D TAB) meetings. Likewise, I am impressed how large EDA vendors (Cadence and Mentor) and smaller ones (ANSYS/Apache, Atrenta, Helic and Invarian) are committed to making the design of interposer- and 3D solutions more user-friendly. Better EDA tools and flows help system- and IC designers to walk the fine line between too costly over-designs and unreliable under-designs.
- Equally important, in my eyes, is the Open 3D TAB’s plan to work with manufacturers and pull detailed 3D materials and manufacturing characteristics together in an “Assembly Design Kit” (ADK) and define the data-formats needed to feed all this essential information into the interposer- and 3D IC planning- and design flows. Just like Process Design Kits (PDKs) contributed significantly to the emergence and success of the fabless & foundry cooperation, ADKs will give a boost to the emerging interposer- and 3D ICs. If you want to express your needs for further improvements of interposer- and 3D IC design and assembly, please give us – within January – your inputs to this Si2 survey.
- Let’s not forget that business models between the different partners in the supply chain still need to be agreed upon and fine-tuned. This, I hope, will also get resolved, as volume production of a number of completed interposer and 3D IC designs will start before end of 2015. The significant number of designs that’s scheduled for high-volume production in 2016 will also exert pressure.
Considering that it takes one to two years to design a “2D SoC” and initially also about that long for getting an interposer or 3D IC design ready for volume production, allow me to urge you: Even if you are not one of the top 10 semiconductor vendors, please invest now in your and your team’s education and analyze what interposer- and /or 3D-ICs can do for your revenues and profits in 2016 and beyond. Talk with your supply chain partners to check what they can offer you to implement one of your designs on an interposer.
Please add your comments & questions for me below, or ask Francoise to connect us for an in-depth discussion. At least, please spend 15 minutes and complete the Si2’s 3D survey to connect with us.
I still remember an engineering VP who was very upset at me, because he lost a big project to a competitor’s ASIC solution. This VP blamed me for not pushing him harder to switch to ASIC technology and train his people on time how to use it. That’s why I am pushing YOU now as hard as I can to consider interposer- and/or 3D-IC solutions for one or more of your 2016 and beyond production volumes! ~ Herb
