IEEE P3405: Chiplet Interconnect Test and Repair Working Group (CITR-WG)
Sponsoring Society and Committee: IEEE Test Technology Standards Committee (TTSC)
Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair.
IEEE Std 1838 does not address this issue. A new working group (WG) has been set up to fill this gap and help enable interoperability to integrate chiplets from multiple design groups. This will make chiplet-based designs more cost effective and reduce development time of complex SoCs.
If you want to participate in this WG and shape the future of the chip design industry send an email to Sreejit Chakravarty (Sreejit_chakravarty@yahoo.com or schakravarty@amperecomputing.com ) with your name and affiliation. The WG meets every week on Fridays between 8am and 9am Pacific Time. Attendance to the WG will be monitored and, in keeping with IEEE TTSC policy, membership will be automatically discontinued if the attendance falls below a threshold. So, please make sure that you are able to attend the WG meetings and also contribute your time outside the WG meetings to develop the standards. Participation in this WG is open to all interested professionals and does not require membership of IEEE or IEEE Standards Association.
