The 56th International Symposium on Microelectronics organized by the International Microelectronics Assembly and Packaging Society (IMAPS) is just around the corner. This year’s symposium will feature five technical tracks, professional development courses and an interactive poster session. The technical program spans three days of sessions with emphasis on SiP/Design/Manufacturing Optimization; Wafer Level/Panel Level (Advanced RDL); High Performance/High Reliability; Advanced Package (Flip Chip, 2.5D, 3D, Optical…); Advanced Process & Materials (Enabling Tech.).
The 3D InCites team will be hosting member companies at the 3D InCites Podcast Booth located in the show entrance area. We are currently recruiting content for the annual Yearbook and as always inviting companies to join our vast network of community members. Additionally, nominations for our 3D Awards will begin. Each year, we celebrate efforts in innovation by hosting the 3D InCites Awards, which recognizes excellence in heterogeneous integration, 3D HI, and chiplet technologies; sustainability; and diversity, equity and inclusion. Nominations for the awards open Monday, October 2.
We have a large number of community members that will be in attendance in San Diego, serving roles as keynote speakers, moderators, presenters and exhibitors.
Member companies scheduled to teach the Professional Development Courses offered on Monday, October 2, prior to IMAPS 2023, are as follows:
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PDC5: 10:30am-12:30pm |
THE EVOLUTION OF FLIP CHIP PACKAGE TECHNOLOGY – Mark Gerber, ASE This PDC course will provide a historical overview and background on the evolution of flip chip packaging as well as short market perspective on this platform. Mobile, Infrastructure, Automotive, High Reliability, Medical and High-Performance Network and Computing all rely on Flip Chip technology to enable their silicon solutions. |
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PDC8: 10:30am-12:30pm |
SIGNAL AND POWER INTEGRITY IN MICROELECTRONICS PACKAGING ANG PHOTONIC INTEGRATED CIRCUITS – Ege Engin and Naim Ahmed, San Diego State University; and Ivan Ndip, Fraunhofer IZM Packaging innovations play a pivotal role in realizing their potential as the demand for compact, high-performance electronics and photonic devices continues to rise. This PDC discusses the electrical design of microelectronics packaging for signal and power integrity and advances and packaging requirements in integrated photonics. |
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PDC9: 1:00pm-3:00pm |
ADVANCES IN FAN-OUT WAFER LEVEL PACKAGING (FOWLP) – Beth Keser, Ph.D. After scale-up and high-volume manufacture of simple single-chip Fan-Out Wafer Level Packaging (FO-WLP) solutions by companies like Qualcomm and Infineon, now many premier semiconductor companies and OEM’s have adopted Advanced Fan-Out structures including Apple, AMD, MediaTek, and HiSilicon. This course will cover the advantages of FO-WLP, potential application spaces, advanced package structures available in the industry, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed. |
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PDC12: 1:00pm-3:00pm |
FUNDAMENTALS OF RF PACKAGING AND HETEROGENEOUS INTEGRATION FOR WIRELESS COMMUNICATION, RADAR SENSING AND HPC – Ivan Ndip, Fraunhofer IZM & Ege Engin, San Diego State University This PDC will briefly present emerging applications in the areas of wireless communication (e.g. 5G, 6G, SATCOM), radar sensing (e.g. for medical, industrial and automotive) and high-performance computing (e.g. for AI). It will introduce RF packaging and heterogeneous integration technologies suitable for the development of components, modules and systems for these applications. |
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PDC13: 3:30pm-5:30pm |
SYSTEM-IN-PACKAGE (SIP) SYSTEM SOLUTIONS THROUGH MINIATURIZATION – Mark Gerber, ASE This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. |
IMAPS DEI Townhall Discussion and Reception: DIVERSITY IN PACKAGING – PAST, PRESENT, FUTURE
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7-8pm This will be a one-hour townhall – open discussion and panel format. Join us for open and lively conversation around many important topics for all to consider in today’s challenging work environment, including the important differences between equity and equality in the workplace. Moderator: Dan Krueger, Honeywell Panelists: Robin Davis, Deca Technologies | IMAPS DEI Chair
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| TUESDAY, OCTOBER 3 1:15-1:40pm Gen 2 M-Series Fan-Out for Chiplet Integration, UCIe, and HBM3 Thermal Performance and Reliability of Liquid Metal Pastes with Solid Metal Particles as Thermal Interface Materials for Computing Electronics Cooling 1:45-2:10pm The impact of Al on contact resistance and its suitability in fine pitch interconnects 2:15-2:40pm Package Assembly Design Kits (PADK’s) – The Future of Advanced Package Design 4:45-5:10pm Evaluation of upscaling the selective electrophoretical deposition of reduced graphene oxide on miniaturized Au interdigital electrodes from chip- to wafer-level A jettable and dispensable liquid metal paste as thermal interface material
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WEDNESDAY, OCTOBER 4
8:15am – 9:00am
KEYNOTE 3: THE NEXT STAGE OF AI: BUILDING FOUNDATION MODELS WIH CHIPLET ARCHITECTURES ENABLED BY HI
Jeffrey Burns, IBM Research
The emergence of Foundation Models is transforming AI. Very large Foundation Models exacerbate computing requirements for AI model inference, fine-tuning, and training. Significant improvements in performance and efficiency are required to address these exponentially growing demands and specialized AI accelerators and systems are needed. A nimble roadmap of ever more capable AI systems requires well-balanced improvement across compute, communication, and memory. Heterogeneous integration and chiplet methods are key ingredients in achieving this balance. In this presentation I will explore the challenges and opportunities in this exciting space, along with some of IBM’s ongoing work to address them.
11:45-12:10 pm A Thermally Enhanced Film Adhesive for Assembling High Power Density Electronic Devices
Yuan Zhao, Henkel Corporation (Douglas Katze, Ana Pre, Derek Wyatt and Josh Sherwood, Henkel Corporation)
1:30-1:55pm Characterisation of a UV-USP laser grooving process combined with plasma dicing to support next generation advanced packaging trends
Rogier Evertsen, ASMPT ALSI B.V. (Janet Hopkins, Oliver Ansell, Samira Kazemi and Richard Barnett, KLA Corporation; Kees Biesheuvel, Jeroen Van Borkulo, ASMPT ALSI B.V.)
2-2:25pm Improving Reliability of Advanced Node Chip Technology in Mobile and High-Performance Computing Applications using Next-Generation Underfill Materials
Gina Hoang, Henkel (Rose Guino, Ramachandran Trichur and Tim Champagne, Henkel)
2:30-2:55pm Using Outlier Control Technology with Feedforward Lithography to Address Die Shifting and Pattern Distortion Challenges in Fan-Out Panel-Level Packaging
John Chang, Onto Innovation (Jian Lu and Timothy Chang, Onto Innovation)
Study on chemical activity of electroless copper plating
Chou I Hsuan, Advanced Semiconductor Engineering (Lai Huei Ting, Chung Yan Wen, Huang Wen Hong, Huang Ming Long, Lin Yue Nong and Fang Ren Guang, Advanced Semiconductor Engineering)
4-4:25pm Photonic Debonding Enabling Applications Beyond Advanced Packaging
Vikram Turkani, PulseForge Inc (Souvik Ghosh, Steven Brems, imec; Luke Prenger and Alice Guerrero, Brewer Science Inc; Vahid Akhavan, PulseForge Inc)
Wafer level chip size package integration of an aero-acoustic MEMS microphone into a thin and flexible substrate
Kolja Erbacher, Technische Universitat Berlin (Piotr Mackowiak and Joao Alves Marques, Fraunhofer IZM
6:30-7:45pm Panel Session on:
THE FUTURE OF PACKAGING FOR ARTIFICIAL INTELLIGENCE
Moderator: Jan Vardaman, TechSearch International
Panelists:
Jeffrey Burns, IBM Research | Director, AI Compute and Director, IBM Research AI Hardware Center
S.P. Jeng, TSMC | Director
WooPoung (Vincent) Kim, Samsung | Corp EVP of Advanced Packaging Group (AVP)
Brett Wilkerson, AMD
THURSDAY, OCTOBER 5
8:15am – 9:00am
KEYNOTE 5: NEW GENERATION ADVANCED PACKAGING FOR HETEROGENEOUS INTEGRATION
C.P. Hung, ASE
Advanced packages deliver the highest density interconnect between chips and are implemented as pivotal enabling technologies for ultrahigh performance module or system. This presentation will explore the design variation, structural difference and developing challenges of the advanced packages for new generation heterogeneous integration to applications on AI server, data center and automotive computing.
9:30-9:55am Trusted data acquisition in microelectronics manufacturing as a basis for ML-optimized processing
Karl-Friedrich Becker, Fraunhofer IZM (Steve Voges, Peter Fruehauf, Matthias Heimann, Stefan Nerreter, Rene Blank, Michael Erdmann, Stephan Gottwald, Andreas Hofmeister, Marc Hesse, Michael Thies, Salar Mehrafsun, Ralf Fust, Eugen Beck, Jakub Pawlikowski, Bernd Schröder, Christian Voigt, Tanja Braun and Martin Schneider-Ramelow, Fraunhofer IZM)
10:30-10:55am Investigating the impact of final finishes on the insertion loss in As Received and after aging
Jobert Van Eisden, Britta Schafsteller, MKS Atotech (Michael Schwaemmlein, Mario Rosin, Gustavo Ramos, MKS Atotech; Erich Schlaffer, AT&S; Michael Gadringer, Ziad Hatab, University of Technology)
Innovations in Type 7 Solder Paste Formulation and Compatibility with Assembly Technology for Sub-75um System-in-Package Applications
Evan Griffith, Indium Corporation
11-11:25 am Cleaning and Particle Challenges in the Temporary Bonding and Debonding Process
Joel Bahena, Veeco PSP (Hunter Jones, Kevin Donnelly, John Taddei, Phillip Tyler, Amit Kumar, John Massey, Seth Molenhour and Yongqing Jiang, Veeco PSP)
11:30-12:30 Poster Session
Mold Void Mechanism with Strip of Molding Gate Ratio Comparison
Tzu Chieh, ASE
Exhibiting Members
| 3D Incites Booth Lobby |
| Ajinomoto Fine-Techno USA Corp. Booth 308 |
| Cadence Booth 408 |
| Deca Technologies Booth 319-321 |
| Finetech Booth 509 |
| FormFactor Booth 418 |
| Henkel Booth 606-608 |
| IBM Booth 701-703 |
| Indium Corp. Booth 229 |
| Mosaic Microsystems Booth 407 |
| MRSI Systems, Mycronic Group Booth 621 |
| NAMICS Technologies, Inc. Booth 506 |
| QP Technologies Booth 203 |
| StratEdge Corporation Booth 218 |
| TechSearch International, Inc. Booth 207 |
