Ever since SEMICON West 2014, I’ve been seeing a lot of coverage of the 2.5D and 3D adoption question on Semiconductor Engineering, an industry content platform that covers the spectrum of semiconductor topics, and occasionally covers 2.5D and 3D, providing the perspective of chip architects, engineers, end users, industry organizations and standards bodies.
What I find most interesting in these recent posts is not so much what’s being said, (because lets face it, it’s pretty much all been said by now) but WHO is saying it. Because Semiconductor Engineering has a direct line into the design world, it’s interesting to see what their take is on 2.5D and 3D, and where they see the remaining challenges. Overall, the design community has yet to be as enthusiastic about 2.5D and 3D as the manufacturing community. However, that seems to be changing.
In his post, All Roads Point Up…But When? SemiEngineering’s Ed Sperling reports his perspective from SEMICON West, He says while it’s clear die stacking is coming, when depends on a number of factors including scaling to smaller process nodes, the state of EUV lithography, and proving 2.5D and 3D IC in volume manufacturing (which is slightly a catch-22 don’t you think?). One point Sperling makes that struck me is that even if EUV arrives, it may be too expensive for all but a few companies to use it. (I’ve also heard it expressed that even if 14nm is alive and well, how many technologies will really require it (read: companies that will be willing to pay for it). Here again, it’s 2.5D and 3D to the rescue.
Brian Bailey interviewed design experts at Synopsys, eSilicon, Kilopass, Synapse Design, Cadence, Mentor and Arteris to get their perspective on when 2.5D will reduce costs. Reading what they had to say, it seems that the cost benefits of 2.5D over scaling to ever-smaller nodes is starting to be acknowledged by chip and system-level architects. There’s also acknowledgement of the technology advantages previously discussed on 3D InCites, such as integrating disparate technologies, building devices at their optimal nodes and stacking them to achieve performance benefits, integrating mismatch-sized components, and integrating photonics. However in almost the same breath, they note that the manufacturing costs of 2.5D and 3D themselves are still too high. Again, as compared to what?
Bailey outlines what the design experts consider to be the four main reasons why cost of die stacking is too high, and provides details on each. They include test, multi-die economics, process issues, and standards. Check out the complete story here.
Another interesting post by Semiconductor Engineering’s Mark LaPedus, Ed Sperling and Katherine Derbyshire, was on the topic of the transition to 450mm. It talks about the overall hold up, reporting on different manufacturers and suppliers. For GlobalFoundries, there seems to be a direct correlation between how 2.5D/3D plays out, and whether they will invest in 450mm. In it, Ramakanth Alapati, director of package architecture and customer technology at GlobalFoundries explains the economics of 2D vs. 3D at various technology nodes and wafer sizes. “A 2D chip on 300mm wafers at 10nm is on par with the cost of a 3D chip,” says Alapati. “When you get to 7nm and 5nm, 3D is cheaper. And the cost of going to 450mm may actually be more expensive. Do we really want 450mm and 7nm if analog and I/O don’t scale?” He went on to explain that at GlobalFoundries, 2.5D will be manufactured in limited volume next year, with a volume ramp in late 2015 and 2016 as yield increases. “If the foundries can bring down the defectivity quickly enough, he said the focus for stacked die will shift away from yield (cost) to performance benefits of this packaging technology. And at that point, 450mm could become a very tough sell to the semiconductor manufacturing industry.”
I look forward to hearing more about this from Alapati during the upcoming panel at IWLPC 2014, System-level Advantages of 3D Integration. I’m also interested in hearing what Mike Gianfagna, VP Marketing at eSilicon, has to say on the topic, particularly after reading a recent guest blog post of his on Semiconductor Engineering titled, 2.5D/3D IC – Do We Have Lift-off. (Spoiler alert if you plan on reading the post) Gianfagna writes “The good news is that this time, liftoff for 2.5/3D IC might be real. There is a definite increase in the number of product plans incorporating this technology.”
All things considered, I’m still betting on 2.5D and 3D ICs. ~ F.v.T.
