The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets.
These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SoC device can be mounted and interconnected in a single package using high-speed/bandwidth chiplet-to-chiplet interfaces. The resulting 3D IC heterogeneously integrated packages deliver greater performance at a reduced cost, and higher yield, and have only a slightly larger area than a traditional monolithic SoC package.
As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the fabless semiconductor industry to standardize on a set of interface protocols that will offer LEGO® like plug-and-play compatibility between different chiplet suppliers, creating a truly open ecosystem and supply chain.
When it comes to the physical heterogeneous integration of these chiplets, it is typically achieved using a high-performance silicon-like interposer substrate. Such substrates typically require silicon-like design rules and design techniques along with their own specific analysis and verification requirements.
The supply chain for these substrates does not change significantly, it is still typically the leading semiconductor foundries and OSATs. However, the level of interaction, requirements and signoff approvals does change, bringing new demands and challenges. Is this a revolution or an evolution, it depends on your starting point? Does it need an entirely new set of workflows and design tools? Can we evolve in some stepwise linear process from where we are today into this next-generation design environment? This paper explores new challenges for 3D IC packaging and outlines five key workflows that address and manage them.
