It probably appears that the only 3D technologies vying for 2D NAND’s crown are V-NAND from Samsung and p-BiCS from Toshiba/SanDisk, with their key selling point being their ability to use few lithography steps to build 3D stacked memory. For background, see Jim Handy’s series and mine.
Here I will discuss the 3D NAND Flash alternative from my company, Schiltron Corporation, that provides a solid foundation for chip capacity increases after 2D NAND silts up; gets to endurance beyond a million cycles; has no vanishing string currents; has no new materials; and can use standard logic fabs without “game-changing” manufacturing equipment.
But first, a preamble to set the scene.
One of the main points about the “litho-light” approaches is the large size of the cell in the 3D stack. Cell size is usually a closely-guarded secret but it was discernible, after calculation, in Samsung’s ISSCC presentation in February this year. The surprising result, published shortly after in my blog, is that Samsung’s V-NAND cell is about 30 times the size of the most advanced 2D NAND cell. Although Toshiba and SanDisk have not said much on this point, there is no reason to believe that their p-BiCS cell size is much smaller since the physics defining the boundary conditions is similar.
Perhaps objectively you could say that this is just a starting point, and that clever engineers will not only stack the cells but also shrink them. Two things however counter this argument. The first came from Samsung themselves at the ISSCC where they stated they would stick with 40nm lithography from here all the way to 1 Tbit. The second comes from an analysis of what is actually defining the pitches of the cell. I also blogged on this but suffice it to say that many parameters define the litho-light cell size per layer and these parameters cannot be easily shrunk since they are defined by other requirements.
Why all this preoccupation with the cell size? Well, it leads us to the age-old discussion in the semiconductor industry, namely, do we add process cost to shrink the chip area to get more chips per wafer and so reduce the chip cost? The answer, at least so far, has been a resounding yes and is indeed the mechanism incorporated in Moore’s Law. The question is, is it still yes when we compare different 3D Flash technologies?
The answer, not surprisingly, is yes. This was the basis of my IEEE Transactions on Semiconductor Manufacturing article where a generic litho-light approach was compared to a litho-intensive approach with 3 masks per device layer. The article dealt with the importance of etch taper angle and vertical gate pitch in defining the litho-light total cost, but anything that makes the litho-light cell larger than what lithography alone could achieve would result in the same conclusion.
Schiltron is precisely that 3-masks-per-device-layer approach. Besides lateral scalability and much smaller cells than the litho-light approaches, we get endurance beyond a million cycles; non-volatile retention at 85°C after endurance cycling; lower voltage program and erase; no vanishing string currents; no new materials; and all possible in existing logic fabs without new “game-changing” manufacturing equipment.
Here’s how.
Figure 1 shows the architecture of the Schiltron concept. The key attributes are: lateral channel in a contactless string of dual-gate devices; one side of the channel (in this case, the top side) has the SONOS dielectric stack for charge trapping; and top gate and bottom gate in each device are independently addressable.
What does this approach allow us to do?
First, the dual-gate architecture allows good electrostatic control. In other words, we can laterally shrink the cell. This comes from the thin channel between the top and bottom gates and the electrical effect that the gates have on shutting off unwanted leakage through the channel.
Second, the first gates in Fig.1 can be driven high to electrically link up any memory cell to the ends of the string. By doing so, we get automatic electrical shielding of any stored charge in the SONOS dielectric stack from the voltage applied to these “passing” gates. This allows us to overdrive these gates to maximize the string currents without any disturbs. It also allows us to decouple the engineering optimization of the SONOS dielectric stack from such disturbs and string current maximization. We can thus use thin tunnel oxide which results in the use of lower program and erase voltages and enhanced endurance. Indeed, there is literature on such classic SONOS reaching multiple millions of cycles
Third, all the steps and materials within each device layer are common to any logic fab. We don’t have unusual aspect ratio etches and material depositions. The alignment of the gates is a fairly standard lithography routine that can be enhanced by adding a bit of overlap to make sure. Figure 2 shows the 3D memory stack along with Transmission Electron Micrographs of the actual devices.
To show the feasibility of this concept, Schiltron built sub-50 nm devices in strings of up to 64 bits and measured their electrical characteristics. Rather than a glossy website façade and some press releases, we chose to publish in the peer-reviewed literature. All of the results can be found in a couple of IEEE publications. If any reader wants more information, do not hesitate to contact me.
What now? Well the industry for the moment seems enamored with the litho-light approaches. Too much has been spent and spoken for the protagonists simply to throw in the towel. There is also comfort to be had by staying part of the pack and choosing to do similar things to what your competitors are doing: if you fail, everyone will probably fail; if everyone succeeds, then so will you. The risks involved with choosing something different encourage executive decision-makers to be highly conservative. That’s just human nature.
We at Schiltron believe that the challenges with the litho-light approaches will only increase with the gradual realization on the part of key decision-makers that alternatives do exist that do not require an over-throw of existing infrastructure and know-how built up over the last 25 years of 2D NAND.
We also have enough industry experience to know that any technology change has risks.
On this last point, that is precisely why we have developed an approach that is evolutionary in critical aspects: allows classic SONOS, a technology that has been used as embedded Flash for over a decade, to be used in a contactless string and in 3D; uses program and erase mechanisms that are well understood; uses existing design approaches to deal with program/erase and natural electrical distributions; and uses existing tools and materials. ~ AJW
