The official inauguration of STATS ChipPAC’s 300mm eWLB facility was held September 15, at the company’s Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating.
In April of 2010, STATS ChipPAC established itself as the first in the world to implement 300mm eWLB wafer manufacturing capabilities. STATS ChipPAC’s robust, automated eWLB manufacturing process which includes wafer reconstitution, wafer level molding, redistribution using thin film technology, solder ball mount, package singulation and testing has proved to be a solid foundation on which the company has rapidly ramped production volumes since fourth quarter of 2009. The company reports having shipped 35 million eWLB units shipped to date.
The transition from 200mm to 300mm eWLB wafer manufacturing was made to provide higher efficiency and economies of scale as compared to the existing 200mm eWLB reconstituted wafer format. STATS ChipPAC’s initial investment in eWLB technology totals more than US$100M.
“We believe eWLB technology is quickly becoming the new advanced packaging solution that more customers are choosing to satisfy the relentless consumer market demand for complex and power efficient semiconductor devices in mobile phones and other handheld electronic products. Our goal is to deliver innovative, cost effective manufacturing technology to customers and help them rapidly ramp to volume production,” said Tan Lay Koon, President and Chief Executive Officer, STATS ChipPAC. “STATS ChipPAC has differentiated itself by our commitment to eWLB technology, from our capital investment to raising the bar on manufacturing efficiency and productivity which directly benefits our customers.”
STATS ChipPAC expects to continue to invest to further expand its eWLB capacity and capabilities over the next three years as the market demand continues to grow for small form factor, small footprint solutions with an increasing number of interconnects. Advanced fab technology nodes drive smaller silicon die sizes with finer interconnect pitches. The eWLB design advantage is that the package size is larger than the silicon die in order to provide sufficient area for the interconnection of the package to the application board. As a result, eWLB has the potential to realize a higher number of interconnects with standard pitches at multiple wafer technology nodes.
