SMTA and Chip Scale Review are pleased to announce the 11th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition (IWLPC 2014). IWLPC brings together some of the semiconductor industry’s most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging.
3D Integration Track
3D Integration and interposer technology are accepted approaches for fabrication of high performance memory-enhanced products, i.e. memory-on-logic stacks. On top of that, 3D integration today is recognized as a key technology for heterogeneous products, demanding smart system integration rather than extreme high interconnect densities.
Heterogeneous integration technologies are being developed for functional diversification systems, i.e. integration of CMOS with other devices, such as analog/RF, solid-state lighting, HV power, passives, sensors/actuators, biochips and biomedical devices. This heterogeneous integration started with system-in-packaging technology, and is expected to evolutionally move to 3D heterogeneous integration with TSVs and wafer bonding. Many R&D activities worldwide are focusing on heterogeneous integration for novel functionalities. Corresponding 3D integration technologies are in evaluation at several companies, research institutions and industrial driven research consortia (e.g. Hybrid Memory Cube, e-BRAINS etc). Furthermore there are significant advances for integrated MEMS systems using 3D integration technologies.
The multitude of abstracts submitted to the 2014 IWLPC evidence the vast activities and interest on the subject matter. The 3D sessions intend to bring you a sample of these advances in Memory Stack, Interposer Technology and TWB Processing among others.
3D InCites Panel Discussion System Level Advantages of 3D Integration
Tuesday, November 11, 2014 | 1:15pm – 2:45pm, Oak Ballroom
For years the industry has discussed and debated 3D integration technologies, discussing the market drivers, technology challenges, supply chain issues, and above all, the cost. As the roadmaps continued to be pushed out, manufacturers, suppliers, and R&D centers have addressed these concerns, and foundries and OSATS have declared themselves ready to ramp production. But still, commercialization lags, waiting for system-level integrators to design in 3D ICs.
In this panel, system-level integrators and manufacturers will face-off in a discussion about the system-level advantages of 3D IC, whether 3D ICs can solve the issues of SoC design complexity and the cost of CMOS scaling to future nodes. The audience will participate in a real-time poll to gauge current industry understanding of these advantages, and the panelists will be invited to present their perspectives on the same polling questions.
Moderator: Francoise von Trapp, 3D InCites, Inc.
- Panelists:
- Rama Alapati, Global Foundries
- Mike Gianfagna, eSilicon
- Belgacem Haba, Google
- Simon McElrea, Energous
- Robert Patti, Tezzaron Semiconductor Corp.
- E. Jan Vardaman, TechSearch International Inc.
