Metrology, process control, and electrical test are key enablers for the success of the semiconductor industry. 3D integration using TSVs offers new challenges in this area that need solutions. There seems to be industry consensus that it is extremely difficult to perform a wafer-level test that ensures the complete functionality of the TSVs. There are ideas about how to perform 3D TSV test with top side contact during standard wafer probe. For example, Giorgio di Natale is proposing to test TSVs by analyzing their RC behavior, which can be done by top side contact and adequate built-in self test (BIST) on the silicon. But all methods are finally incomplete tests, as, for example, defects that are very close to the inner end of the TSVs cannot be detected.
TSMC has therefore created a new acronym for TSV wafers that have gone through electrical wafer test: it is no longer known good die (KGD) but pretty good die (PGD). And they say it is a big challenge to test 2.5D interposers including TSV functionality before bonding dies on top of them. The reason for this difficult TSV testability with wafer probe is contacting a 50 – 100µm thin waver from both sides.
Companies like Advantest and Cascade Microtech are developing solutions to contact micro bumps or very fine pitch sacrificial test pads. These solutions are heavily needed to test Wide I/O Memory stacks before they are shipped from the memory maker and bonded onto interposers or micro-processors in another factory. But any time the thinned wafers (after TSV reveal) are processed, one side is completely shielded by either a Thin Wafer Support System (TWSS) or sawing tape. So there is simply no physical access to both sides. And it seems to be the nature of a 50 – 100µm thick and 300mm diameter piece of silicon, that it needs full back side support any time it is handled.
So there are processes needed that enable double side contact test before other chips are added onto the bottom die. Multitest has developed and proven a solution to test partial stacks, which consists of Die on Substrate (DOS) – with TSVs on the backside, by contacting onto the substrate I/Os. The microbumps and sacrificial test pads on the other side are physically accessible in this DoS setup. So the feasibility of full TSV functional testing (before adding additional dice onto the bottom die) seems to be more realistic in this process flow than in a CoWoS (Chip on Wafer on Substrate) flow.
Adding the micro contacting solutions from Wide I/O memory testing to the CoS (Chip on Substrate) test process plus micro contactor alignment plus new double side signal routing and processing methods can provide a solution to achieve Known Good Partial Stacks (KGPS). There are at least no physical hurdles to be overcome.
I strongly believe that a partnership with members from device design, foundries, OSATs, tester companies, contacting technologists and handler specialists is able to develop such a solution, that can be applied and add value in the complex 3D TSV industrial manufacturing and business environment. ~ B.L.
