So here I am in Honolulu with my family, celebrating the return of my nephew from a 6 month deployment on a nuclear submarine, and I realize that the co-located IEEE Symposia on VLSI Technology and IEEE Symposia on VLSI Circuits is taking place at the SAME TIME, and there’s a couple of sessions on 3D technologies!! So rather than joining my gang on a scuba diving adventure, I send them off to explore the ocean depths and take myself over to the Hilton Hawaiian Village to check out the 3D action. (Ok, this isn’t exactly how it happened, but it makes for a good story, and most of it is true.)
VLSI (which stands for very large scale integration, I looked it up) includes programmable logic devices, design tools, embedded systems, etc. Companies established in VLSI fields include Texas Instruments, Infineon, Cadence, Synopsys, Celox Networks, Cisco, Micron, National Semiconductors, ST Microelectronics, Qualcomm, Mentor Graphics, Analog Devices, and Intel; some of the same big players in the development of 3D integration technologies. So it was only a matter of time before 3D integration sessions would appear on the technical agenda, particularly in the joint sessions; another nod to the fact that 3D integration requires true collaboration across the spectrum of semiconductor manufacturing from wafer processing through back-end assembly.
I attended the joint session on Memory in the morning, where Joe Jeddeloh’s presentation titled Hybrid Memory Cube New DRAM Architecture Increases Density and Performance caught my eye. He explained some of the basic architecture of the hybrid memory cube (HMC) and the low power and bandwidth benefits that are the result of this structure. What’s most exciting, he said, are the possibilities for partitioning technology in a different manner than before. Essentially, the idea is to begin by removing the logic from the DRAM, thereby stripping it down to just the memory. This allows the DRAM to be optimized for power. The common circuits are moved to the logic layer, which allows the DRAM to be simplified and parallelize. The DRAM is partitioned into banks and stacked using TSVs. “TSVs allow us to create more parallel, concurrent resources (banks).”
I asked about concerns with connecting the DRAM to the logic without an interposer. Were they worried about putting TSVs through the active area of the die? Here’s how they handle it: rather than having a big TSV pattern in the center of the logic die, they create the interface between the logic and the DRAM stack at the edge of the logic die by putting SERDES devices around the edge of the logic die, and using a crossbar switch to ship the data to the edge where interface circuits are located.
The goal was to create a building block that could be used in multiple situations. With regards to interconnecting this DRAM/Logic block to the processor will be application specific. Different solutions may require different materials to send signals through. It’s critical to find the one that is most power-optimized. “If you can change the distance to the processor and the topology, it becomes a power optimized solution,” he said, alluding to photonics as being a an important tool to address the distance over the long range, and it could come into play in HMC Generation 2.
Jeddeloh said Micron, IBM and about 90 other companies are part of the HMC consortium, dedicated to bringing it to market. Micron provides the memory, and IBM handles the logic and manufacturing. When I asked about remaining challenges he said that this is a new assembly process. The TSVs look good, but they haven’t manufactured the device in volume yet. Assembly and yield can’t be determined until you run millions, he explained. But he doesn’t anticipate any specific issues, and expects HMC to be available next year.
I spent the early part of the afternoon in the session on 3D Integration, and of the four presentations, two of them focused on the topic of TSV stress, with slightly different findings. Jeff West, of Texas Instruments, kicked off the afternoon with a presentation titled, Practical Implications of Via-Middle Cu TSV-induced Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect, followed by Thermal Stress Characteristics and Impact on Device Keep-out Zone for 3D ICs containing TSVs presented by Paul Ho, of the University of Texas, Austin.
West explained that TI has programs using TSVs in both analog and digital technologies, and this was the first time the company presented its findings on TSVs 28nm CMOS. (The analog work is all internal). The company has followed the JEDEC path of Wide I/O DRAM on logic because it has multiple suppliers and multiple customers, so it’s important to stick to standardized processes.
While modeling TSVs in active die suggested potentially more stress issues due to the TSVs, West reports TI experienced a different outcome with practical implementation. He said they did work to examine the proximity effect of placing transistors at different distances from the TSVs, and discovered that the impact is “quite small when compared with other care-abouts.” In fact, he said other context-dependent sources for a typical 28nm layout are much more significant to the transistor than the TSV is. “It turns out TSVs are the least of our worries with regard to being contributors to stress in 28nm devices.” he reported. An approach TI is using with regard to keep out zones (KOZ) is to use the space for such passive devices as ESD protection circuits and capacitors so that there’s no need to place the transistors near the TSVs. In this case, it becomes a design strategy.
Paul Ho seemed surprised by the outcome of TI’s work, and commented on it during his presentation. He noted that stress problem for TSV are well known, and that the origin is the coefficient of thermal expansion (CTE) mismatch between copper and silicon. While West focused on silicon stresses in his presentation, Ho drew the attention back to copper, where there are concerns with stress at the interface between copper and silicon, and with TSV pop-up.
Citing work with via-mid processes, Ho said stress is a classic materials problem, and TSV stress is 3D in nature, with distinct near-surface characteristics that can be solved with what he called a “super position method.” He talked about the KOZ, and noted that it increases with the TSV diameter and height. He also talked about the effects of Cu plasticity “If you can control the chemistry, you can relax the stress.” he said. For the future, as you scale down TSVs, you will reduce the near surface stress.
Ho concluded by referring back to the TI presentation, saying “they are so confident they don’t have a problem, but they may have to worry a little bit about stresses.” He said they have to look at how the whole structure is affecting the electrical property and electrical migration, and stress plays apart in all of those.
And with that, I decided to call it a day. I am, after all on vacation and I think it’s time for a Mai Tai – Mahalo everyone! ~ F.v.T
