Day Two of 3D ASIP and even though the conference opened with declarations that “3D is here” it’s clear after attending the sessions and hearing what all the presenters have to say, that this is a multi-dimensional situation. First, there are the vendors and suppliers, who have a lot at stake, having invested billions developing processes to get to this point. Then there are the manufacturers — IDMS, Foundries, and OSATS —who see the potential and are investing in capital equipment to be ready when that first order comes; and lastly, but most importantly, there are the customers (fabless, fab-lite and end-users) who, at the end of the day, really cast the deciding vote as to whether (or more likely when) this goes or not.
Here’s where everyone seems to agree – 3D is the way to solve future scaling issues. When we say “3D is here” what we really mean, is ‘The NEED for 3D is here.” Douglas Chen-Hua Yu, from TSMC said that with all the debate and argument surrounding 3D, you can’t argue that there is a paradigm shift from device scaling to system scaling, and that the industry has been re-defined by mobile computing. He talked about chip-package interaction (CPI), which refers to the stresses exerted by packaging materials on low-k dielectrics on the chip, causing cracks and damaging IC performance; and how CPI gets worse with scaling. Altera’s Bradley Howe predicted that there are 8-10 years left to scaling, and then 3D will be the solution. “3D makes way for new classes of products. They can bring more processing power, and that’s a good thing.” He noted. Like Xilinx, Altera manufactures FPGAs, and Howe says FPGAs are already heavily integrated, making them prime candidates for 3D. LeiLei Zhang, of graphic chip maker NVIDIA, was even more direct in her comments. “Scaling is ending. Let’s get over it (EUV) and move resources elsewhere.” 3D perhaps?
The only phrase repeated more frequently than “3D is here” was “there is work left to be done.” Remaining challenges cited by all (several presenters offered the caveat at the start of their talk with “what I’m about to say will only reinforce what you’ve already heard”) include: supply chain infrastructure; EDA tool readiness; thin wafer handling coupled with temporary bond and debond; standards; liability ownership; yield; and at the top of the pile: COST. By the end of the conference, some of those concerns were addressed by presenters from the various research institutes, EDA vendors, and equipment and process suppliers (especially the temporary bond and debond issue) indicating that these challenges are lost on no one and are being addressed as rapidly as possible.
With regard to supply chain solutions; it appears there will be more than one option here, as all the big players want a piece of the pie. While Yu built a good case for a pure foundry model, claiming to have made progress in critical areas for 3D IC manufacturing (TSV, low-k Cu, and advanced bump and assembly) and declared that TSMC was ready to take on manufacturing from end-to-end, Yole’s Jeff Perkins pointed out that there’s lots of money in play here, and other people aren’t going to just walk away, but are going to look for alternative solutions. Jan Vardaman pointed out TSMCs successful collaboration with Amkor on the Xilinx project, and asked if there wasn’t a way TSMC can work in partnership with OSATS who already have skills required. Yu said the days of TSMC dealing with other players is in the past. “It’s a new ballgame and the risk is too high.” He said. “We don’t want to deal with that. The old way of doing business is out of date.” Ok. So I guess that would be a solid “no”. Talk about drawing a line in the sand.
Likewise, Dan Berger of IBM talked about the supply chain challenge and how IBM is also suited to handle the end-to-end manufacturing. He said the company’s approach requires a continuous feedback loop, which helps to drive down costs and improve yields. That isn’t as likely to happen when the hand-off is between different outsourced companies. IBM has experience and understanding of all these elements. “From that perspective,” he noted, “it’s good to be an IDM.”
But when it comes to fabless customers who want to combine chips from various sources, a foundry/OSAT model might be the more viable solution, and STATS ChipPAC’s Raj Pendse says the company is ready to handle that. He outlined the company’s capabilities – mid-end through back-end assembly, ready to process thick wafers that are easier to handle in transport. “By changing the way packaging is done, it impacts our knowhow and business model.” He said. “This is something we’re managing quite well.”
And that brings us to the ultimate question: what does the customer want? 2.5D? Full blown 3D? Foundry/OSAT model options? Turnkey solutions? Is the risk too high? Are the challenges remaining too significant to move forward? We can talk about these things all day long, but at the end of the day it’s the customer who decides, and it all depends on their needs. There are those willing to take the risk, and those who still prefer the more conservative evolutionary approach. It remains to be seen which path will prove to be the most profitable at the end of the day.
In her presentation, LeiLei Zhang was quite pointed about NVIDIA needs “Bandwidth. We need it. It’s not there.” She said the company will take a stepped approach to the solution, starting with a 2.5D passive interposer based product She’s one who thinks 3D still has a long way to go and issues to be resolved. “2.5D allows more time for true 3D product development.” She also said that NVIDIA is likely to use a turnkey solution such as TSMC is offering, or foundry/OSAT with the wafer hand off while it is still at full thickness.
Qualcomm is one fabless who has opted to leapfrog over the 2.5D and put their money on full blown 3D through silicon stacks (TSS). Urmi Ray, senior staff engineer at Qualcomm, said the company investigated its own market sector, and determined form factor and performance to be the most critical elements to fulfill company needs, and that the best performance in the smallest form factor comes from the direct 3D stack. She said technology challenges have been solved in the prototype levels and now need to be solved in volume production levels. “These are not fundamental physics problems,” she said. “They are engineering problems and engineering problems usually get solved.” Qualcomm supports MEOL processes at the OSAT. And when asked by Jan Vardaman why then do we have to wait 2 more years for a product introduction from Qualcomm? (Jan knows how to get straight to the heart of the matter, doesn’t she?) Rayi’s quick response and ultimate message to manufacturers: “Get the cost down and we’re ready to announce products.”
Ray used a marathon analogy to describe where we are with 3D. “The technology is in the last mile stage, we know we’re going to get there. We will finish it.” She said. Given the time of year, I like to compare it to Christmas, it’s coming whether or not we’re ready for it, and everyone is scrambling to get those last items on the list. How many more shopping days left? ~ F.v.T.
PS:Check out yesterday’s in-depth article in EE Times on TSMC. While it might have been more aptly titled “TSMC Would Like to Go it Alone with 3DIC, Rick Merritt captures the discussion well.
