Today’s side trip to the GSA’s 3D EDA Interest Group’s bimonthly meeting (sandwiched between IEDM 2011 and RTI’s 3D Systems Integration Conference) proved to be worth the trip for several reasons, but particularly for the “behind the curtain” glimpse at Xilinx’s stacked silicon interconnect technology that was introduced to the market several weeks ago.
Arif Rahman, principal engineer and technology architect at Xilinx explained the advantages of this 2.5D side-by-side integration that delivers the capabilities of multi-chip FPGAs in a the model of a monolithic FPGA. Here’s how it’s done: multiple FPGA “slices” are bonded face down on a passive silicon interposer. Microbumps connect the slices to the interposer. TSVs with C4 bumps then connect the interposer to the package substrate.
According to Rahman, the side-by-side die layout has a minimal heat flux issue and minimal design tool flow impact. Stress simulation tests showed that the interposer makes the device more reliable because it functions as a stress buffer, reducing low- k stress and stress on C4. Additionally, it improves C4 bump reliability. Rahman says this technology, which was developed in collaboration with IMEC, SEMATECH and SEMI, is well on its way to volume production.
Silicon interposer technology is also being leveraged by ASE to stack and assemble different technology chip from its foundries and customers. Calvin Cheung, VP of engineering at ASE Group said that the company sees many applications for interposer technology including integrating them into next-generation package-on-package (PoP) configurations due to requirements getting thinner with closer pitch requirements (100µm pitch and 150µm between silicon interposer and package substrates; and stacking logic/memory next to RF and MEMS devices on a silicon interposer in a heterogeneous configuration. “Silicon interposers aren’t merely a stop-gap technology,” noted Cheung. “We see long term value for silicon interposers.
The interposer technologies was just one of many technology developments inside ASE that Chueng used to illustrate the challenge of standardizing such varied configurations. However, it’s clear to Cheung that some sort of standardization is necessary for the supply chain.
“What we need for 3D IC standards are the ones that are beyond what we have now for standard flip chips,” explained Cheung, adding that the issues exist in IC design, foundries and OSATS. While no particular standard is needed for modules, a set of specifications in which multiple parties can participate, such as equipment, would be beneficial. The needs shall be identified from technical issues that concern interoperation in the supply chain. “Test issues are what keep us up at night,” he noted as an example of an area that would benefit from standards. The short answer is that we all need to work together to develop 3D IC standards.
These speakers were just part of the GSA EDA 3D Interest Group’s bi-monthly meeting. The purpose of the gathering was several fold – to keep the EDA community up to date on the progress of 3D IC and to encourage participation in the 3D IC work groups Herb Reiter is assembling as part of a 3D IC task force. 3D InCites will continue to work with the GSA in promoting this effort and spreading the word. – F.v.T.
