My recent visit to EV Group at its headquarters in Schärding, Austria, included some time spent with M. Jürgen Wolf, who, as part of his management and coordination of Fraunhofer IZM-ASSID (All System Silicon Integration Dresden) is the program & project manager for 3D Wafer Level System Integration (WLSI) and wafer-level packaging (WLP). There’s been a lot of activity going on with Fraunhofer’s 3D program, and it was time I learned more about it. Lucky for me, he was also eager to speak with me, and even re-routed his trip home from San Francisco to Berlin through Munich to do so. As EVG recently announced their partnership with Fraunhofer IZM-ASSID, it was a fitting place to get together. Ironically, as it turns out, SPTS (which I also visited) will install the company’s first Pegasus DSI at Fraunhofer IZM-ASSID. AMAT, and other suppliers start to install new equipment at ASSID as well.
Before diving deep into technical waters, Wolf brought me up-to-date on some organizational changes within the Fraunhofer IZM’s 3D program that up until now, was an activity between Berlin and Munich. He said due to some upper management changes, Fraunhofer IZM-ASSID as part of Fraunhofer IZM is operating out of its Dresden location, which was previously a Quimonda facility and all activities are aligned within Fraunhofer´s network in Saxony and Germany.
Wolf’s team has been busy converting from 2D to 3D processes, and 200mm to 300mm equipment. He’s now happy to report that the grand opening has taken place and their process setup started with 300mm TSV formation equipment – sputter, etch, CVD, lithography, ECD, and wet etch among them. Thinning, backside processing, and various assembly processes will take place in a different spot, but work is underway there as well to outfit the 1000m2 cleanroom. The partnerships with EVG, SPTS, AMAT and other equipment and material supplier are part of that.
Fraunhofer IZM-ASSID’s overall vision is the heterogeneous integration of different chip functionalities into one wafer-level system-in-package (WLSiP) by using enhanced 3D TSV and thin chip integration, assembly and interconnects technologies. What’s different about Fraunhofer’s approach, notes Wolf, is that rather than working on each process step independently of the next, they’re taking a process integration approach from the system perspective to get a better idea of how it will all work together, rather than having to flip back and forth, tweaking one process so that it works better with the next. The main technologies being developed in this manner include:
- TSV formation (etch, isolation, barrier, filling)
- Silicon interposer technology with high-density multi-layer metallization
- Wafer thinning and handling
- Temporary wafer bonding and debonding
- Die-to-wafer assembly and wafer-to-wafer bonding
- 3D stack formation
According to Wolf, technology targets include TSVs filled with copper rather than tungsten, driven by interposers with high-density multilayer redistribution layers and intergrated circuits (ICs). They’re working on a 3D design and reliability model with an integration that includes via-mid process (via formation before back-end-of-line (BEOL) processes).
Interposers are a key element in the program, and different strategies are being examined, such as interposers with devices embedded in the redistribution layer (RDL), and stacking interposer elements that use TSVs between embedded die with a flip chip stack on top.
In the via fill area, Wolf says they’re working on high speed, void-free copper filling and reducing overburden total thickness after the filling. The goal is to develop and qualify processes for high density Cu-TSVs with a diameter of less than 5µm up to 80µm and a depth of 20µm to 600µm.
Temporary support scenarios for thin wafer processing are driven by the need for low-profile 3D configurations, explained Wolf. Some of these include thin IC on a thin substrate, thin IC on a thin interposer, and a thin IC stack on thin interposer. Some of the concepts include temporary wafer bonding on a handling substrate, and temporary support for thin die assembly. This is where the collaboration with EVG comes in, working on perfecting the room temperature debonding process that we’ve been hearing about. I got to see the bonding tool being built specifically for Fraunhofer. Markus Wimplinger, of EVG explained it to me and we happened to catch it on video.
Also part of this is the advanced chip to wafer bonding technology that involves a two step process for high throughput, in which known good die (KDG) are placed using a temporary bond and then the permanent bond is done in a gang process.
I’m really barely touching on all that’s going on there. Suffice it to say that the main message Wolf hoped to spread about Fraunhofer IZM-ASSID is that the organization is committed to working together with industrial customers. The key is combining technology developments with availability, manufacturing and reliability aspects. “Cost matters,” notes Wolf, “so all processes are aligned to high yield and cost savings without losing performance.”
At the end of our visit, Wolf and I were both heading back to Munich, so he graciously offered me a ride. It was great to get some additional time for further explanation. I realized this is the first time I’ve ever written specifically about Fraunhofer’s 3D activities, but I suspect it won’t be the last. — F.v.T.
