Ok, I’m annoyed. I just read an article (thanks for pointing me to it Gretchen Patti) that appeared last week in EE Times, Is TSV Ready for Prime Time or Not? reporting VSLI’s research presented at IITC a few weeks ago . I find some of VSLI’s “observations” extremely infuriating, because once again, they’re making assumptions based on historical comparisons based on the time it took older technologies to make the big time. Not to mention, the article contains some glaring inaccuracies.
First of all, experts don’t define 3D PACKAGING as stacks interconnected with TSVs only. 3D packaging, as we’ve preached ad nauseum here, comes in many flavors, such as package-on-package (PoP) already in volume production, as well as chip stacks that are wire-bonded, or use alternative interconnects like VCI’s jetting technology. LETI has a whole program focused on non-TSV 3D configuration. It is in manufacturing 3D ICs (or as some define it 3D silicon) for high density applications that can’t sufficiently be served by wire bonds or other interconnect technologies that TSVs are expected to dominate.
Next, CMOS image sensors (CIS) are NOT the only technology in production using TSVs. (Note this was VSLI’s claim, not EE Times.) Silicon interposers also use TSV for interconnects, and although alone are not a 3D structure, they are being used for interim 3D stacking solutions in 3D systems-in-package. And let’s not forget about MEMS, the pioneer application for TSVs. According to Robert Castellano, of the Information Network, (who, by the way, wrote an excellent rebuttal article to this, TSVs: Ready for Prime Time?) in 2009, over 50% of TSV wafers produced were for not for CIS. Furthermore, Castellano states that by 2013, memory will overtake CIS as the leading application in the TSV market, reaching 30% and that the TSV market will increase tenfold in the next three years.
In my opinion, assumptions shouldn’t be based only on Intel’s roadmap. Yes, they’re still looking for the killer application, but although they may be one of the big guys, they’re not the only game in town. ST Micro, IBM, Elpida, TSMC, Samsung, Toshiba, ASE, UMC, and others have thrown their hats in the ring, formed alliances, and are going full steam to iron out all those kinks.
And finally, it’s time to stop beating the EDA-tools-are-not-ready drum. Pay attention. Mentor, Cadence, Synopsis – all on the case, in addition to a host of smaller design tool houses. Likewise, the test community is working on test standards, and processes are being tweaked, etc, etc.
Of course, TSV is not ready for prime time – TODAY. The fact that there are still challenges to be faced until full market adoption of TSVs happens is really old news. What is news, in my opinion, is that almost DAILY, new developments are being announced that demonstrate these challenges are being addressed. So I would say, ready or not, here they come.
I’ve said my piece. I feel much better now. – F.v.T.
