Did you hear the news about Elpida? They’ve announced they’re moving forward with commercialization of 3D TSVs. According to an interview with Elpida’s CTO Takao Adachi, published yesterday on Semiconductor International’s website and written by Phil Garrou, the company is shifting from a poly-Si filled TSV to a metal TSV. They have a 300mm line in place with a 10,000 wafer capacity, and plans to complete qualification in 2010 and begin shipping devices. Interestingly, they intend to use a via-last approach, copper metallization, and die-to-die stacking. Target applications include DRAM and heterogeneous stacks of memory with both RF and Logic devices. The heterogeneous devices might also involve silicon interposers in the stacking process. Additionally, Garrou reports Elpida’s targeting 30 µm pitch, 30 µm wafer thickness, all for less than $100/wafer.
While many of you may be thinking, wait – why via last and not via middle for these applications? Why die-to-die rather than die-to-wafer or wafer-to-wafer? Why copper when there are still so many reliability issues? And what about test? I’m thinking there’s a logical progression going on here. These developments validate what the R&D guys at Leti and IMEC have been telling me all along. It’s about following the path, leveraging processes that are most accessible and doable now with little change to existing processes, thereby involving the least risk. User confidence is already established. It makes sense to leverage that momentum.
I think it’s also safe to assume that Elpida’s not revealing the whole story. They must be pretty confident about their yields and reliability concerns to be moving forward with this. This way, they get to be first. Everyone else will be next. And while they’re shipping product, they’ll be busy behind the scenes ironing out the remaining wrinkles in the other processes so that when the time is right, they can be first with those too. Not bad, Elpida. Someone’s got their thinking caps on. – F.v.T.
