One of the questions plaguing all of us waiting for the adoption of TSVs for 3D IC stacking is what’s the hold up? We’ve been hearing about IT for so long, we’re straining forward in our seats ready for take off. But it’s complicated. While equipment and material processes have been proven to achieve sub $200/wafer cost, with $150/wafer as the next target, there are still limitations to be addressed, namely EDA tools, thermal management materials and processes, and test.
The quarterly issue of iMicronews’ Advanced Packaging Newsletter arrived in my inbox today, and coincidentally two articles shed some light on progress with two of these limitations. Paul Magill’s Wanted: Thermal Management Materials for 3D ICs explains Nextreme Thermal Solutions approach for using thermally active copper pillar bumps for acive side, back side and lateral cooling. In Will 3-D EDA Tools be Ready in Time? Sally Cole Johnson queries execs and design engineers at IBM, CEA Leti, R3Logic, and Cadence for answers to that million dollar question. (NOTE: If you’re one of those people who gets upset when someone tells them how the book ends, don’t read any further.) The conclusion? Mostly smoke and mirrors. All we know for sure is that they’re working on it.
