As May rolls right into June, so do the 3D events; or should I say events in which 3D topics are addressed. Indeed, it seems as if 3D is permeating just about everything. From looking at the programs, it’s clear that organizers are struggling with categorizing presentations to fit under one categorical umbrella. Oftentimes, while there are dedicated tracks, there’s overflow into others. Another thing to note are those presenters who are “doing the circuit” so-to-speak. If you’re fortunate enough to be attending more than one of these events, you can maximize your conference time by being aware of possible re-runs.
June 2-4 IMEC Technology Forum 2009
Celebrating it’s 25th year, IMEC has re-christened the Annual Research Review Meeting (ARRM) to IMEC Technology Forum (ITF). While the event will cover the gamut of IMEC’s work, specific to 3D technologies will be Eric Beyne’s presentation on heterogeneous integration,and how it will require advances in 3D technologies including: through-Si-via connections, ultra-thin die thinning, high density interconnect die stacking and die embedding technologies. Following Beyne’s presentation, Ingrid De Wolf will address metrology, test and reliability challenges brought on not by 3D chip stacking, also for co-integration of MEMS on top of CMOS and other heterogenous configurations.
June 14-17, The Confab, Las Vegas, NV
Of particular interest to those of us following 3D IC integration issues, will be the session at Confab on Tuesday, June 16, 2:15 PM – 3:45PM titled Economic Implications of Test. In light of test complexities brought on by 3D IC integration such as redundancy, KGD issues, built-in self-test and repair, etc., speakers will address the economic scalability of the test roadmap over the next 3 to 5 years, by examining test drivers, test flow simplification, and “Test Lite” philosophy.
June 15-18, EMPC 2009, Rimini, Italy
European Microelectronics and Packaging Conference (EMPC), combines the efforts of IMAPS Europe; IEEE Components, Packaging, and Manufacturing Technology Society (CPMT); and iNEMI into one biannual event. This year’s event is jam-packed with 3D. Of specific interest to me will be Rao Tummala’s tutorial and subsequent keynote, Beyond 3D ICs to 3D Systems. Additionally, each member of the EMC3D consortium will give a presentation as part of its tutorial session on Monday, June 15. On Thursday, two of the advanced packaging sessions will be devoted to 3D packaging, in addition to 3D related presentations scattered throughout the program as they apply to other categories such as Hannes Kostner’s presentation in the flip chip track, Impact of 3D Packaging Technologies on Flip Chip Equipment; Fraunhofer’s contribution: 3-D Packaging Concept for Cost-effective Packaging of MEMS and ASIC on Wafer-level; to name only a few. Trust me, you won’t run out of things to do at this one. Plus who can resist Rimini in June?
June 28-July2 2009 Lithography Workshop, Coeur d’Alene, Idaho
Historically, this even focused on leading-edge lithography. This year, presentations will include advances in 3D architectures and packaging. A panel discussion, moderated by Dan Hutcheson, debating the pros and cons of advanced lithography vs. advanced packaging and 3-D structures (taller vs. smaller) will be held on Wednesday evening, July 1, 2009.
That wraps it up for June, with the Big Kahuna – SEMICON West, right around the corner. No doubt that event will get a post or two all of its own. Stay tuned. – F.v.T
