Sponsored by The IEEE Council on Electronic Design Automation and The IEEE Computer Society of Silicon Valley, The 24th annual, IEEE Electronic Design Process Symposium takes place at SEMI Headquarters, Milpitas, on September 21-22, 2017.
IEEE EDPS 2017 Program focuses on acceleration methods for the design and manufacturing processes. The event will be held at the SEMI facility and provide a forum for EDA, foundry and design industries to address the design and the manufacturing issues. Emerging trends like machine learning and big data analysis and their impact on the above-mentioned issues will be addressed. The full two-day program features prominent speakers from industry and academia in multiple domains including:
- Design Acceleration
Rajesh Gupta, John Lee, CP Hung and Bill Bottoms - Driving to Higher Yield
Keith Arnold, Asim Salim, Gerard John, Juan Rey - Accelerating Debug & Validation
Gajinder Panesar, Eduardo Bolanos, Al Czamara, Vikas Kumar - Machine Learning
Paul Franzon, David White, Rob Aitken, Jeff Dyke, Abhijit Chatterjee
Keynote speakers include:
- Antun Domic, CTO, Synopsys
Exploit close relationship of design & manufacturing to accelerate product intro - Zoe Conroy, Sr. Manager, Cisco
Using System level testing as a conduit to HVM - Jim Hogan, Private Investor
EDA industry’s participation in cognitive age: The fourth industrial revolution - Pankaj Mehra, VP, Western Digital
Getting EDA ready for the data centric architecture
We will conclude with a panel discussion to analyze new directions for accelerating design and manufacturing processes. A complete schedule is available at ieee-edps.org. Early registration and discounted rates will close on August 31. To register, please go to edps2017.eventbrite.com.
