The Great Divide Between Semiconductor Design and Manufacturing

Shortly before the summer break started, I attended a number of industry conferences: MEPTEC, ECTC, DAC, MEMS & Sensors, ASME and SEMICON West. At all of them, I clearly noticed that our industry is looking beyond “Moore’s Law” to advanced IC packaging, multi-die ICs, and system scaling.

However, at every one of these conferences, I also noticed the “Great Divide”: It’s difficult to spot EDA experts at IC manufacturing-focused conferences and vice versa. EDA conferences, like DAC, attract very few – if any – IC manufacturing experts. This Great Divide between semiconductor design and manufacturing needs to be addressed now because both camps increasingly have to rely on each other’s cooperation to make our move to “More than Moore” a mutual success.

Some current and most future market requirements won’t be satisfied by following “Moore’s Law” and offering single-die, individually packaged, primarily digital system-on-chips (SoCs). For many applications, the current SoCs will need to become die-level IP building blocks for integration into multi-die ICs and (sub)systems. Markets like Internet of Things (IoT), wearables, mobile devices, automotive and industrial applications don’t want components. They need (sub)system-level solutions. In addition to digital logic, they require these (sub)systems to include functions like analog, RF, memory, MEMS, sensors and others, to interface with the real world. To successfully design and manufacture such complex, multi-die solutions we’ll need to make some changes. In addition to the already well working cooperation between SoC designers and wafer fabs, these designers – who are mostly electrical engineers – also need excellent support from our industry’s assembly / packaging experts, who are mostly mechanical or chemical engineers.

What can we, especially our industry organizations, do to bridge this Great Divide?

Based on what I learned in previous roles, I suggest that education, training and working together on trailblazing projects, will be needed to get both design and manufacturing experts to understand and appreciate each other’s knowledge and skills and establish best practices for how to jointly create cost effective multi-die solutions for a broad customer base.

In addition, the currently segment-specific industry conferences need to invite more presenters and attendees “from other sides” and cover a larger part of the supply chain. Also, our industry organizations need to expand their work in support of vertical and horizontal cooperation, as the following examples demonstrate:

• The Electronic System Design Alliance (a.k.a. ESD Alliance), formed last year by the EDA tool vendors to refocus our industry’s efforts from TRANSISTOR scaling to SYSTEM scaling. The ESD Alliance has already taken a big step towards addressing this Great Divide between the semiconductor design and manufacturing community. They published the Multi-die IC User Guide last June. This guide, according to readers’ feedback, is the most comprehensive document about multi-die IC technologies and supporting capabilities across the entire supply chain. It is available as a soft copy only, and contains many web pointers to relevant topics and almost 500 pages of general information about the multi-die IC related capabilities of 35+ companies in our semiconductor ecosystem: EDA and IP vendors, assembly houses (OSATs), IC materials and equipment vendors, R&D and industry organizations, market research experts as well as services companies have contributed. This guide shows electrical engineers what is available for manufacturing of multi-die solutions. Likewise, it shows mechanical and chemical engineers how design tool and methodologies assist designers to create multi-die solutions and what kind of materials and manufacturing data these tools need, so they can produce viable results in a timely manner.
• Starting this September, the ESD Alliance will take another step towards bridging this Great Divide by holding regular meetings of the pre-competitive System Scaling Working Group (WG) to bring together IC design experts and EDA tools vendors as well as IC manufacturers and their suppliers. They’ll encourage the WG members to outline their requirements and capabilities for each other, discuss general market trends and opportunities, their impact on the semiconductor industry and how we need to respond. This WG will also suggest best practices for solving system scaling challenges with multi-die solutions in a timely manner and cost effectively. Examples for likely WG topics are a) An efficient die-package CO-design flow, b) Exchange formats for encrypted design and manufacturing data, c) Accurate modeling of IC material characteristics, and d) high-level modeling of “chiplets” = IP building blocks in die form. If you see value in joining this WG, to outline requirements and contribute ideas, please contact herb@eda2asic.com.
• You may have heard already that the industry-wide cooperation for bi-annual updates to the ITRS roadmap has ceased to exist. The authors published their last report on July 8, 2016. To continue industry-wide planning efforts, CPMT, SEMI and EDS are sponsering a new, more appropriate effort, called: The Heterogeneous Integration Roadmap. Please contact your SEMI representative to learn more about this program and the plans to make the efforts outlined above synergistic.

Clearly, after 50 years of following “Moore’s Law”, continued feature size shrinking is no longer the path to prosperity unless your SoC design serves an extremely high-volume application. The change to “More than Moore”, combining heterogeneous functions in a small form factor, is finally in full swing and requires significant changes at individual companies and to the semiconductor ecosystem overall.

All industry conferences mentioned above have emphasized the importance of advanced IC packaging technologies, to combine multiple heterogeneous functions in a single IC.

Semicon West conveyed the need for change best – as indicated by this year’s theme: DEFINITELY NOT BUSINESS AS USUAL.

IMEC’s presentations during the ITF USA event (a partner event to SEMICON West) are always impressive. This year they conveyed that feature size shrinking to about 3nm, using vertical nanowires appears feasible, however, they did not comment on the economics of 3nm designs. Several speakers also mentioned IMEC’s efforts in support of 3D ICs and explained the need for system scaling. Luc Van den hove showed how after the PC, the smartphone/applications wave impacted innovation. Now the IoT wave will be a large growth opportunity for our industry. He also confirmed what I heard from others: IoT edge nodes will contain significantly more silicon than originally expected. Some local computing and program/data storage will be needed, to consolidate the vast amounts of sensor-generated data to useful information and minimize the bandwidth needed to transmit this information to a hub and/or data center for further use.

Cisco’s keynote on Tuesday morning, presented by John Kern, started out with a few impressive numbers: In 1994 only 23 million people were connected to the internet. by 2014 this had grown to 3 billion. In the next few years, another billion people and 10 billion devices will be added to the IoT.

To enable this rapid growth, IoT providers need to learn how to address electrical, mechanical, chemical, biological and other multi-physics / chemistry / biology challenges and combine hardware, software, and services to provide valuable solutions for our customers.

Semiconductors account today for 60% of Cisco’s cost of goods and Kern mentioned that 2.5D ICs, especially to combine electrical and optical functions on the interposer, look very attractive to Cisco. 2.5D ICs increase performance while decreasing power dissipation and size of Cisco’s networking equipment.

Denny McGuirk, SEMI’s president and CEO, moderated Wednesday morning’s panel discussion between executives from Entegris, Intel, Lam, and Qualcomm. Their key message was that “Co-opetition is now more important for than ever before.” Co-opetition is defined as “collaboration between business competitors, in the hope of mutually beneficial results.” The key takeaways included:

• Today’s equipment with stand-alone embedded systems will be connected to the Internet.
• As the cost of sensors and connectivity declines, the 50B IoT edge nodes will contain 200B sensors by 2020.
• Silicon components will be a small part of IoT; services and solutions revenues will be larger.
• Two-thirds of today’s wafer fab capacity is for > 65nm products.
• New materials, design, and manufacturing flows will enable much lower power ICs.
• A restaurant chef without taste buds is unimaginable; so will be our world without sensors.
• More collaboration and sharing of info AND rewards is needed to achieve new business models.
• Today’s component suppliers need to become solutions providers.
• Performance per Watt is a key differentiator; power management IC (PMICs) are gaining importance.
• Design & manufacturing cooperation can significantly narrow the yield distribution and lower cost.
• Mergers and acquisitions are good for our industry; they pool patent portfolios & talent and drive economies of scale.
• The continuously increasing need for more memory is a great opportunity for our industry.
• Co-opetition is key for our industry; SEMI should drive more.
• IoT needs co-opetition because it will enable new players (e.g.Uber) and trigger other valuable solutions.
• New partnerships and business models are needed; e.g. an Amazon.com-like player in the semiconductor ecosystem.

The bottom line: Semicon West and the other manufacturing-centric conferences I attended recently demonstrate that equipment vendors, interposer wafer foundries, material suppliers, OSATs and services providers are ready for the paradigm shift to More than Moore. They are all waiting for more multi-die IC designs.

When I talk to potential multi-die IC designers, I hear that we are waiting for:

• User-friendly design tools and methodologies and
  • Lower unit cost.
  • Close cooperation between materials, manufacturing and EDA experts to create “assembly design kits” (ADKs) that offer accurate and current data that enable EDA tools to produce accurate and valuable outputs. Just like process design kits (PDKs) enabled the fabless and wafer foundry business model to grow, ADKs are needed to enable a mutually beneficial multi-die IC design and manufacturing cooperation. Several promising programs have started already to address this point and will become highly visible in 2017.
• Our component cost comparisons to change to system cost approaches, e.g. also consider that:
  • Multi-die ICs’ lower power dissipation results in smaller power supplies, lower cooling cost, cheaper batteries and smaller mobile devices.
  • The smaller footprint lowers cost of printed circuit boards, connectors, cables, and mechanical components.
  • Multi-die ICs enable higher system performance, a higher selling price, and better margins.
  • At least one comprehensive system cost analysis, outlining how to apply a total system cost perspective, when using multi-die ICs, is in progress and will be published before year-end.
•  IC design tools, having accurate and up-to-date data, enable designers to walk the fine line between costly over-design and risky/unreliable under-design of ICs and (sub)systems.

That’s clearly the biggest cost-reduction opportunity we can utilize as soon as we bridged the Great Divide with some high returns on investments.

On a personal note: Market acceptance of multi-die ICs is progressing in a similar way as I have experienced when working on the bleeding edge of FPGAs and ASICs. In a few years, multi-die ICs will be the third “must have” technology for every successful IC and electronic systems vendor. ~ Herb       .