Device of the Year
Amkor Technologies, Inc: SWIFT
SWIFT: uniquely developed to deliver a high yielding, high-performance package with the thinnest profile in the industry. This package can deliver 2um line/space lithography with up to 4 layers of RDL and a very dense network of memory interface vias from bottom package to top package at a very cost competitive price. Due to the nature of fabrication, the package provides a path during processing for known good die to known good die site placement, virtually eliminating the risk of high value die loss during the product build. This is a key distinguishing feature that also allows for significant reduction in cycle time by fabricating the RDL prior to die arrival for assembly and also ultimately improves overall cost by maximizing the yield during fabrication.
OSAT of the Year
NANIUM
NANIUM’ is a world-class provider of advanced semiconductor packaging, assembly, and test, engineering and manufacturing services. The company is a leader in 300mm Wafer-Level Packaging (WLP), both Fan-In/ WLCSP, but mainly Fan-Out/ WLFO based on eWLB technology. NANIUM is well recognized in the packaging community worldwide and was awarded by several of its customers and co-operation partners emphasizing the high level of engineering and innovation creating leading-edge packaging solutions such as FOWLP based WLSiP and WL3D. NANIUM is the largest OSAT in Europe and strongly engaged in activities strengthening this part of the Semiconductor Supply Chain. NANIUM is co-founder and chair of the ESiPAT Group (European SEMI integrated Packaging, Assembly, and Test Special Interest Group).
Supplier of the Year
Invensas (A Tessera Company)
Invensas Corporation operates as a subsidiary of Tessera Technologies Inc. With this year’s acquisition of Ziptronix Technology and the integration of its DBI® process into the Invensas product line, Invensas now offers the industry’s highest density, smallest footprint, lowest profile and lowest cost 2.5D and 3D IC integration platform to address the upcoming 2.5/3D-IC market growth. DBI is a low-temperature hybrid bonding technology with interconnect capability with the potential to be the industry’s finest pitch, thinnest and lowest total cost-of-ownership 3D integration solution for wafer stacking and Die-to-wafer 3D stacking using low-cost metallic materials such as Cu without micro-bumping. It eliminates micro-bumping and significantly reduces the cost of 2.5D and 3D production. Finer bond lines achieved using DBI® also helps to reduce device footprint, which can lead to increased productivity.
Fabless of the Year
Invensas Zibond and DBI Technologies
Invensas technologies Zibond and DBI are at the forefront of enabling the adoption of wafer-to-wafer, die-to-die and die-to-wafer bonding in the volume production of image sensors, MEMS, 3D IC and other semiconductor packaging applications.
Zibond is a low temperature homogeneous (oxide to oxide) direct bonding technology that forms strong bonds between wafers or dies with same or different coefficients of thermal expansion (CTE). The technology uniquely addresses the need to transfer material grown on a particular substrate, for lattice matching or process development to another substrate, for improved device performance.
DBI is a low temperature hybrid direct bonding technology that allows wafers, or die, to be bonded with exceptionally fine-pitch 3D electrical interconnect. DBI can minimize the need for Thru Silicon Vias (TSVs) and Thru Die Vias (TDVs) by forming interconnects at the bonded surface.
These advanced low-temperature bonding technologies enable reduced manufacturing stress and enhance device reliability compared to other conventional bonding techniques, while also providing lower cost-of-ownership.
Engineer of the Year
Bryan Black and AMD’s engineering team
AMD’s use of a silicon interposers with 65,000 TSVs and a logic die in the center of four HBM stacks with four DRAM each represents a major engineering achievement. Fiji has 4X bandwidth improvement per watt over AMD’s Radeon™ R9 290X. It has a 4,096-bit memory interface with four stacks creating 512GB/s of bandwidth, which is 60 percent more bandwidth than the Radeon™ R9 290X.
The new architecture required 8.5 years of R&D, engineering, and product ramp. The massive engineering effort included technical core competence development of micro-bumping, middle-end-of-line (MEOL) TSV fabrication, assembly, and test solutions. A total of 20 different company and government organizations were involved in working on the project. Demonstrations in conjunction with the Fraunhofer Institute in Germany assisted in the development of the tool infrastructure. The complexity of die stacking involved many factors that could only be analyzed and addressed by building functional prototypes.
Research Institute of the Year
Fraunhofer Cluster for 3D Integration
The Fraunhofer Cluster for 3D Integration is represented by the Fraunhofer IZM-ASSID, Fraunhofer ENAS, Fraunhofer IIS/EAS, Fraunhofer IKTS, Fraunhofer IPMS
… for their fundamental work in 3D Heterogeneous Integration for the realization of Smart System in Package in the era of Internet of Things (IoT). Each institute in the cluster delivers a holistic approach to the design, development, and implementation of 3D heterogeneous systems for industrial applications from demonstrator development up to prototyping and low-volume manufacturing
The Fraunhofer 3D Cluster looks at the system from all perspectives from functionality, design, technology, performance and reliability and provides an integrated solution as a system integrator. The complete value chain is available inside the cluster to serve the customer for a successful 3D solution. The cluster is also involved in various projects supported by the European commission e.g. MASTER 3D, CarrICool, ADMONT – each institute bringing its very own expertise into the project and in this way generating valuable synergies to create and validate new technical and technological solutions.
Lifetime Achievement Award
Phil Garrou
For the insights that he provided via his blog, his involvement in the IEEE 3D-IC and RTI 3D-ASIP conferences and For publishing the first series of Handbooks on 3D ICs.
