Sadly, this year it was the 3D session track that had lots of empty seats at the 2015 International Wafer Level Packaging Conference (IWLPC 2015), which was a bit surprising since 3D is really hitting its stride with so many products in high performance computing on the market. Next door, however, the fan-out wafer level packaging (FOWLP) session was a sold-out show. Both the keynote by GlobalFoundries’ Rama Alapati, and Jan Vardaman’s FOWLP panels were standing room only.
“We are all chasing a rabbit called FOWLP,” said Vardaman, “The purpose (of this panel) is to keep us from going down the rabbit hole.” This particular “rabbit hole” is panelized processing, vs. wafer, and whether or not this is the right direction for FOWLP. As such she lined up panelists from many of the major OSATS that are in the FOWLP business including John Hunt, AS; Curtis Zwenger, Amkor; Tim Olson, Deca Technologies; and Jose Campos; Nanium. Beth Keser provided insight from Qualcomm as the customer, and Thomas Uhrman, EV Group, as the voice of the equipment supplier.
Why all the FOWLP hoopla? Lots of reasons according to Alapati, who described FOWLP as falling somewhere between an evolutionary and disruptive technology, providing improved performance without shaking up the existing OSAT infrastructure or supply chain. “Revolution is too strong a word,” he noted, commenting on his presentation title, High Density Fan-out: Evolution or Revolution? “The invention of the transistor was a revolution. It changed how we live and how the future has changed.”
Alapati said that while traditional FOWLP has the potential to replace flip-chip chip-scale packages (FCCSP) and ball grid arrays (BGAs), High Density Fan-out (HD-FO) challenges interposer-based technologies in performance and signal to noise ratios. Alapati classified Infineon’s embedded wafer level BGA (eWLB) as a traditional FOWLP. Amkor’s SWIFT and SLIM, SPIL’s NTI and SLIT, and TSMC’s InFO fell into the HD FO categories. Deca’s M-Series wasn’t on Alapati’s radar, but would also be classified as HD FO.
Where HD FO can replace incumbent technologies depends on the applications, noted Alapati. One advantage of HD FO is that it allows for multi-die integration, and disintegration of SoC (This is a very familiar story. Isn’t it?). In the case of HD FO vs. FcCSP; HD FO alone is cost and performance neutral compared to TMV PoP, but has significant power and area savings.
Interposer was a big draw in high performance applications because it solved issues with interconnect delay, time to market yield, and package module reliability risk. HD FO technologies like SLIM, SLIT or INFO eliminates through silicon vias (TSVs) and the Si substrate to offer better signal to noise ratio, and could provide a better solution not because of dollars saved, but because it provides improved performance options for disintegrating die and co-packaging, explained Alapati.
“Silicon interposer technology has its space; when we need tens of thousands of interconnects between die, and aren’t concerned about noise and signals going off chip, the interposer plays well,” he said.
Will FOWLP Panel Processing Happen?
With such great potential for FOWLP in high volumes, there’s been lots of discussion about the advantages of moving to panelized processes for production as a way to further reduce manufacturing costs. This was the topic tackled by the panel, in addition to the chips-up vs. chips-down comparison.
Surprisingly, most of the panelists weren’t in a hurry to transition to panelized processes for reasons that included availability of manufacturing equipment and the cost of developing such tools, as well as the inability to define a standard panel size or material. Is it square or rectangular? Do we go with laminate or compression mold? Is it a substrate or fab process? What are the design rules and what yield would you need? What about warpage concerns? There were more questions posed during that discussion than answers. My question was, if the front-end can’t develop a 450mm infrastructure with their higher profit margins, how can we expect the OSATs to finance a panel infrastructure if we can’t even decide on a standard size and format?
“If we had a panel line today, we couldn’t fill it,” noted Hunt. Campos concurred, and added that at Nanium, they see no technical advantage to moving to panels. The same features can’t be achieved and there’s less flexibility in designing complex modules. Additionally, he said a move to panels would require design rules to be relaxed.
Offering the perspective of the equipment manufacturer, Uhrman said it’s a “costly and painful” effort to scale up equipment to bigger than 300mm. He is not expecting many companies to expand to panel, as they are more interested in leveraging tools that are already installed. “The whole infrastructure for panel is missing, and it’s not possible to achieve 5µm line/space on panels.” Although Keser said that if FOWLP is 15µm l/s at 95% yield, they will put it in a panel, achieving sufficiently fine line and space is a critical element when going up against interposer technology for the same market space. Currently, most of the FOWLP manufactures report 10µm line in space in production, with many in qualifications for 8µm, 5µm and sights set on 2µm, which is the magic number.
Olson was the only panel member enthusiastic about panelized processing for FOWLP. But perhaps that’s because Deca Technologies’ fab was built off of SunPower, using large format Si wafer processes on non-traditional fab equipment “We are capable of building large things in excess of 700mm.” said Olson. “We are currently building 300mm round panels, but the equipment is readily scaled to a larger format,” he said. He added that 300mm is sufficient capacity for now, but the company expects it will be 2 years before they need a panel line. “Without the promise of cost structure, most people won’t design into panels,” he noted. On the line/space topic, Olson says most of Deca’s current production is at 10µm l/s, and they have qualified processes at 8µm and some at 5µm. He added that they’ve done feasibility studies for 2µm, and thanks to the company’s proprietary adaptive patterning technology, expects to be able to achieve 2µm on panels in two years.
On the topic of chips up vs. chips down, panel opinions and justifications varied. Hunt said that ASE is currently working on six different versions of FOWLP, and in some cases chips down is the best approach while in others, chips up wins. At Deca, the simple answer is chips up, noted Olson, because it supports many things, including advanced lithography required to achieve 2µm l/s on large panels, and makes integration with Cu studs eaiser. It also helps die attach cost, because its tolerant of high speed chip shooters and is not force sensitive.
Other topics the panel touched on included warpage issues, materials, the importance of cleans, die placement systems and the roadmap for vertical interconnect – because yes, while HD FO will challenge interposer integration, going vertical is part of the roadmap.
So while we are chasing FOWLP down the rabbit hole, the question remains, at the end of the day, will that hole lead to a new path for 3D integration? ~ FvT
