Multi-die systems are driving the need for standardized die-to-die interconnects. Several industry alliances have come together to define such standards:
- Optical Interface Forum (OIF) – The XSR and USR physical layer specifications optimized for die-to-die connectivity
- Chips Alliance – The AIB specification which was originally introduced by Intel
- Open Compute Platform (OCP) – The OpenHBI and Bunch-of-Wires (BOW) specifications optimized for different use cases
- Universal Chiplet Interconnect Express (UCIe) – A comprehensive die-to-die interconnect specification covering multiple use cases and a complete protocol stack
The UCIe standard was introduced in March of 2022 to help standardize die-to-die connectivity in multi-die systems. UCIe can streamline interoperability between dies on different process technologies from various suppliers.
UCIe Board members are shown above. There are currently 130 member companies globally.
Defining UCIe Standard versus UCIe Advanced
Recently Manuel Mota, Principle Product Manager for Synopsys loaded a webinar and several presentations on the web comparing UCIe Standard vs UCIE Advanced. Review this information to better understand what UCIe is about.
UCIe defines PHY variants for Standard (S) (standard organic substrate / laminate) and Advanced (A) packages (silicon interposer, silicon bridge or RDL fanout):
- UCIe-S has coarse bump density and floorplan aligns with density limitations of standards packages
- UCIe-A with dense floorplan takes advantage of high routing / bump density
Both options share the same architecture and protocols. The only difference is in bump map and PHY organizations. This difference means that system architecture, system validation, and software development can be re-used regardless of the chosen package type for a particular SoC.
The UCIe specification is divided into three stack layers (Figure 2) Physical Layer, Die-to-Die Adapter Layer and Protocol Layer.
Physical Layer is the electrical interface to the package media. It includes the electrical AFE (transmitter, receiver) as well as a sideband channel to enable parameter exchange and negotiation between two dies. It also includes the logic PHY, which implements the link initialization, training and calibration algorithms, as well as test and repair functionality.
Die-to-Die Adapter layer takes care of link management functionality as well as protocol arbitration and negotiation. It includes the optional error correction functionality which is based on a CRC and retry mechanism.
Protocol Layer implements one or several of the UCIe-supported protocols. Today, such protocols are PCI Express, CXL and/or streaming that are Flit-based protocols, offering maximum efficiency and reduced latency.
Protocol Layer
UCIe maps common protocols, like PCI Express and CXL, enabling developers to leverage previous work on software stacks and simplify the adoption of in-package integration using multi-die architectures. UCIe expects standardization of other protocol mappings in its future releases.
Die-to-Die Adapter Layer
The Die-to-Die Adapter Layer is an intermediate layer that interfaces any protocol to the UCIe PHY Layer.
UCIe 2.0
The UCIe specification 2.0 standard was released in Aug of 2024.
The 2.0 Specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures (Table 4). UCIe-3D is optimized for hybrid bonding with a bump pitch functional for bump pitches as big as 10-25 microns to as small as 1 micron or less to provide flexibility and scalability.
Another feature is optimized package designs for interoperability and compliance testing. The goal of compliance testing is to validate the main-band supported features of a device under test (DUT) against a known-good reference UCIe implementation. UCIe 2.0 establishes an initial framework for physical, adapter, and protocol compliance testing.
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