TSMC recently announced at its Open Innovation Platform (OIP) Ecosystem Forum in Europe that its chip-0n-wafer-on=substrate (CoWoS) packaging technology will achieve certification by 2027, introducing a version with 9x reticle size.
This will allow twelve HBM4 memory stacks, providing unprecedented performance enhancements for artificial intelligence (AI) and high-performance computing (HPC) chips. If certified in 2027, it is expected to be utilized in high-end AI processors between 2027 and 2028.
The CoWoS technology was first launched in 2016, initially featuring a package size of approximately 1.5x. Today, CoWoS has evolved to 3.3x reticle sizes, capable of accommodating eight HBM3 stacks.
TSMC anticipates employing system on integrated chip (SoIC) vertical stacking logic chips to increase transistor count and performance. For instance, within the 9x reticle package, customers can stack 1.6nm process chips on top of 2nm chips.
TSMC has committed to launching a 5.5x reticle package between 2025 and 2026, which will support up to twelve HBM4 stacks (Figure 1)
However, ultra-large CoWoS packages face challenges related to substrate size and heat dissipation. For example, the 5.5x reticle version requires a substrate measuring 100x100mm, while the 9x reticle version exceeds 120x120mm. The large substrate sizes will impact system design and data center configurations, particularly concerning power supply and cooling systems. In terms of power consumption, high-performance processors may reach several hundred kW per rack, making liquid cooling and immersion cooling technologies more effective for managing dissipated heat.
TSMC is on track to qualify its ultra-large version of CoWoS that will offer an interposer size of up to nine reticle sizes and 12 HBM4 memory stacks in 2027. The new packaging method will address the most performance-hungry applications and let AI and HPC chip designers build processors the size of the palm of a hand.
TSMC introduces new process technologies every year, doing its best to meet its customers’ needs for power, performance, and area (PPA) improvements. But some customers need even more performance, and for whom an EUV litho tool reticle limit of 858 mm^2 is not enough. These customers choose to use multi-chiplet solutions packaged using TSMCs CoWoS technology, and in recent years, the company offered multiple iterations of this method.
The original CoWoS enabled chip packages of around 1.5-reticle size in 2016, then evolved to 3.3-reticle size today, which enables placing eight HBM3 stacks into a package. Next up, TSMC promises 5.5-reticle size packages with up to 12 HBM4 memory stacks in 2025 – 2026. However, this pales behind the company’s ultimate version of CoWoS, enabling system-in-packages (SiPs) of up to nine reticle sizes with 12 and potentially more HBM4 modules onboard.
That 9-reticle ‘Super Carrier’ CoWoS (offering up to 7,722 mm^2 for chiplets and memory) with 12 HBM4 stacks is planned to be qualified in 2027, so it is reasonable to expect it to be adopted in 2027 – 2028 for ultra-high-end AI processors.
TSMC fully expects companies adopting its advanced packaging methods to also vertically stack their logic using its system-on-integrated chips (SoIC) advanced packaging technologies to further boost transistor counts and performance. In fact, with 9-reticle CoWoS, TSMC expects its clients to place a 1.6nm-class die on top of a 2nm-class die, so we are talking about very high transistor density.
However, there is a major challenge with those ultra-large CoWoS packages. The 5.5-reticle CoWoS package will require an over 100×100 mm substrate (which is approaching the size constraints of the OAM 2.0 standard, which measures 102×165mm), whereas the 9-reticle CoWoS will go beyond a 120×120 mm substrate. Such major substrate dimensions will have an influence on how systems are designed and how data centers are equipped to support them. In particular, power and cooling. When it comes to power, we are talking about hundreds of kilowatts per rack, whereas when it comes to cooling, we are talking about liquid cooling and immersion methods to manage high-power processors effectively.
Amid the booming AI business, TSMC has been aggressively expanding its CoWoS capacity. Production targets for 2024–2025 are set to more than double consecutively, yet demand continues to outpace supply. TSMC is expected to complete construction by March–April 2025. Equipment installation is slated for the second half of 2025, with production contributions beginning later that year. TSMC is also reportedly negotiating to acquire a second facility. Meanwhile, its Chiayi fab is targeting equipment delivery by the end of 2025 and installation in early 2026, focusing on SoIC expansion, with production potentially starting by late 2026.
IFTLE Question – Since one of the drivers for glass interposers has purported to be the ability to manufacture larger dimension substrates, does this silicon capability by TSMC to go 9X reticle put more pressure on those favoring glass in the future due to size requirements?
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