Installation of High NA EUV at Intel - Source Intel

The CHIPS Act continues to issue grants to help advance the United States position in semiconductor and advanced technology. Two CHIPS for America R&D facilities were announced in late October and early November. First announced was an $825 million dollar grant to Albany Nanotech in upstate New York to develop an EUV accelerator to go along with the rest of the advanced semiconductor technology center already in place.

CHIPS for America R&D facilities The other grant, the size of which was not mentioned was for a second CHIPS for America Research and Development facility in Sunnyvale, CA, the heart of Silicon Valley. This is one of three CHIPS for America research and design facilities and will operate as the headquarters for the National Semiconductor Technology Center (NTSC) and Natcast which will be the operator of the center.

The facility is classified as an American Design and Collaboration facility (DCF). Set in what was once the hotbed of semiconductor development, the DCF will lower the barriers to semiconductor prototyping, experimentation, and other R&D activities that will support America’s global strength and leadership in design, materials, and process innovation while enabling a vibrant domestic industry. This will include:

  • Conducting advanced semiconductor research in chip design
  • Electronic design automation (EDA), chip and system architecture, and hardware security
  • Hosting programmatic activities, including the NSTC Workforce Center of Excellence
  • Design Enablement Gateway, and a future Investment Fund
  • Convening NSTC members and stakeholders from across the semiconductor ecosystem
  • Housing various administration functions

I have had at least one discussion if this might have been the best location due to the cost of living. However, if the center is to be focused on EDA and chip design, 2 of the 3 top EDA companies are in close proximity, with the third up the coast in Portland. There is also a considerable amount of AI chip design taking place in Silicon Valley, and there is easy access to Stanford and Berkley, which have well established programs in semiconductor technology.

The placement of the EUV center in Albany was likely an easier decision. Albany has had and EUV program ongoing since 2003 when Sematech, with IBM support, started the EUV project in Albany with the first system being shipped in the 2006-time frame. The first commercial EUV systems to move into production in the US have just recently taken placed with the installation of two High NA EUV tools at Intel in Oregon. (Feature image: FInstallation of High NA EUV at Intel (Source: Intel)

The facility in Albany is tasked with giving the US semiconductor industry:

  • Access to cutting-edge EUV lithography tools and next generation R&D capabilities, including high numerical aperture (NA) EUV systems, with standard NA EUV expected by 2025 and High NA EUV in 2026.
  • Convening and spurring collaboration with industry, academic, and government partners to advance technological innovation.
  • Dedicated NSTC on-site offices to support Natcast and NSTC member researchers
  • Support for programs that provide, foster, and grow a talented workforce
  • Efforts to grow NSTC membership and engagement while fostering an open, collaborative R&D environment with all NSTC facilities

Most of the above is available at IMEC using the ASML EUV and High NA EUV tools installed there, but IMEC is focused on a world-wide industry, not specifically the US. This is also bringing back EUV technology to the U.S., which is where it was first developed before ASML took on the gargantuan task of bring the technology to life. It will be interesting to see how this plays out.

It will also be interesting to see who has access to the technology, as at the moment Intel is the only U.S. company that has chips that need EUV. GlobalFoundries would potentially benefit, but that comes with a big price tag that they have backed away from in the past. Since both of these programs have a focus on workforce development there should be a considerable amount of academic work using these tools.

There is a third CHIPS for America R&D facility to be focused on advanced packaging that has yet to be announced. It will be interesting to see where this one lands. There are several possibilities, Arizona, Indianna, Portland and New Mexico all have advanced packaging activities in place, but since politics are involved, there are many places this site could be placed. I will be interested to see what happens first, the posting of this blog, or the announcement of the last CHIPS for America R&D facility.

Dean Freeman

Dean W. Freeman, Chief Analyst at FTMA, has over 36 years of semiconductor manufacturing and…

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