Nanosheets, Superpower rails, 3D Fabric, SoW, along with N2, N3, 16A, and 14A. Enough acronyms and numbers to make your head spin. All of these terms and more were discussed at the TSMC 2025 North America Technology Symposium in Santa Clara, held in late April. TSMC holds this event annually to update its progress and let its customers and partners know where they are headed over the next few years. According to the presentations, TSMC produces semiconductors for their clients, accounting for $250 billion of the $656 billion semiconductor market in 2024. TSMC is forecasting that when the semiconductor market reaches the $1 trillion mark in 2030, it will account for $500 billion of that market. Thus, moving from having a part in manufacturing 38% of the world’s semiconductor revenue to 50% of the semiconductor market.
That is a bold statement with potential competition on the horizon, but a realistic one, as TSMC continues to position itself as a trusted technology and capacity partner with a dependable technology cadence.
As Dr. Kevin Zhang laid out the market outlook, he pointed out that AI and high-performance computing (HPC) will account for over 45% of semiconductor revenues in 2030. While that is lower than the 59%, they reported in their Q1 earnings call, it demonstrates the continued strength of the HPC/AI market over the next 5 years. TSMC pointed out that as AI and HPC continue to grow, energy-efficient computing, reducing power consumption, and helping the semiconductor industry meet its sustainability goals will be driven by the advancement of silicon technology and product-level optimization using advanced packaging. Zhang discussed foundry 2.0, which has been brought up several times in TSMC earnings calls, where the foundry model has transitioned from building non-packaged chips and shipping those chips to OSATS for packaging, to now building complex multi-chip systems using advanced packaging and delivering those products to their customer. This is driving up the value of the final product, which is one reason why a $1 trillion semiconductor market is within sight by 2030.
The 2N node is TSMC’s next technology node, which is rolling out in the second half of 2025. 2N is TSMC’s first node where they will use nanosheet or Gate All Around (GAA) transistors. Samsung already is using nanosheet transistors in production, and Intel’s 18A technology, which also uses nanosheet transistors, is rolling out around the same time as TSMC.
The 3N node was also highlighted as TSMC rolls out chips for its different customers. This will be TSMC’s last technology node using FinFETs. FinFETs were first introduced into production at TSMC in 2014 at 16nm, so the 3N FinFETs are the 10th anniversary of TSMC using FinFETs. TSMC will be producing multiple variations of the 3N technology to provide for AI and data center, CPU, mobile technology, automotive, and other value technology types.
TSMC is waiting until the 16A node to introduce a technology called backside power. TSMC is calling this the super power rail. There are several different marketing names for backside power circulating in the industry. The process increases overall process complexity but helps to reduce process complexity in the metallization layers by moving them to the backside of the wafer. The drive to the backside power is because it helps to reduce power consumption and improve power distribution, which are critical areas for chips that need to reduce power consumption and provide higher performance. TSMC mentioned that the next insertion for backside power will be at the second generation of 14nm.
Dr. Yuh-Jier Mii discussed future technology that builds on the nanosheet transistors. Moving from FinFETS, to nanosheet, to CFET, then into 2-dimensional gate technology. The development of these next-generation 3D transistors will require a significant amount of both material and process technology. This ensures that faster and more powerful transistors will continue to emerge in the future to support advanced technology.
TSMC has been manufacturing the FinFET for approximately 10 years. It will be interesting to see how long it will take the transition from nanosheet transistors to CFET and then to two-dimensional technology.
TSMC used the technology forum to lay out their 3DFabric packaging roadmap. 2.5 and 3D packaging has become a highly competitive space, and with HPC/AI and automotive systems all highly dependent upon advanced packaging. The move from mostly manufacturing transistor technology into a world that includes advanced packaging into systems, has launched what TSMC has referred to as foundry 2.0.
Dr. Zheng and Dr Mii both discussed the today and tomorrow platform for HPC/AI. Figure 3 shows the additional complexity of the Tomorrow platform. The package of tomorrow will have multiple logic chips stacked and connected, along with the HBM required for low latency. The interposer, whether using silicon or RDL technology, will have embedded components to help with power management and package operations. System-to-system communications will be performed with Co-packaged optics, which will improve latency, use less power, and create significantly less heat in the package.
The need for higher-performance chips in AI is also driving the industry to multi-reticle packages. The TSMC roadmap has the industry using 9x reticle packages in 2027, which in turn is driving panel-level processing needed for higher yields and better manufacturability.
To support the move into foundry 2.0, TSMC is expanding its packaging capabilities rapidly. In addition to the five advanced packaging facilities, TSMC is already operating, the company has two advanced packaging facilities announced in the United States to support its expansion in AZ, and announced two more in Taiwan in Chiayi.
TSMC is running like a well-oiled machine. Its performance over the years, as well as consistently delivering on a well-publicized technology roadmap, makes it easy for its customers to commit to partnering with TSMC. While there is competition building in the foundry and advanced packaging space, TSMC’s execution of its plan makes it easy to believe that they just might be responsible for 50% of the semiconductor revenue in 2030.
