Advanced packaging has emerged as a critical enabler of next-generation applications for artificial intelligence (AI), high-performance computing, wearables, 6G communication, and defense technologies. As traditional scaling approaches face increasing limitations, Advanced packaging enables further miniaturization and improved performance through heterogeneous integration, chip stacking, and high-density interconnects.
In Europe, advanced packaging has emerged as a strategic focus in the region’s ambition to build a resilient and self-sufficient semiconductor ecosystem. With significant investments under initiatives such as the European Chips Act, the goal is to drive semiconductor innovation, focusing on R&D, packaging and manufacturing to enhance Europe’s technological sovereignty and supply chain resilience.
Following the grand opening ceremony of our facility and Advanced Packaging Competence Centre in Barbing, Germany, we hosted a webinar on February 25th as a chance for an international audience to gain insights into the latest developments in advanced packaging in Europe.
Driving innovation in Europe
Debbie-Claire Sanchez, Head of Advanced Packaging Equipment Solutions at ERS, kicked things off by addressing the elephant in the room: Why invest in Europe? The answer was clear—with initiatives like the European Chips Act, Europe is strengthening its semiconductor ecosystem, and ERS wants to contribute to bridge the gap between research and production, support regional semiconductor growth, and accelerate innovation by offering local support.
At the new ERS Competence Center, visitors can explore and test cutting-edge advanced packaging solutions designed to tackle real-world manufacturing challenges:
- Warpage Adjustment Tool: A solution designed to minimize handling-induced warpage in wafers and panels up to 650 x 650 mm, helping manufacturers maintain stability throughout the production process.
- Wave3000 3D Wafer Profiler: A tool that maps wafer warpage across different handling stages, giving manufacturers critical insights into process variability.
- PhotoThermal Debonding: Developed in collaboration with PulseForge, this innovative debonding method simplifies the Temporary Bonding and Debonding (TBDB) process by eliminating the certain process steps, reducing both time and cost
With Competence Centers in Germany and Shanghai, and additional locations soon to be announced, ERS is committed to expanding access to advanced packaging technologies, not only in Europe but to manufacturers worldwide.
Electronics Packaging in Europe – Growing or Vanishing?
Steffen Kröhnert, Founder of ESPAT-Consulting, had just returned from the Electronic Components and Systems (ECS) Brokerage event in Brussels and brought some valuable insights. While Europe’s role in electronics packaging has historically been limited, he highlighted how the region is gaining momentum, thanks to strong policy initiatives and industry collaboration.
Steffen presented two of the three pillars that make up the European Chips Act:
- R&D and Pilot Lines: Investments in design platforms and competence centers aim to give European users and companies better access to electronic design automation (EDA) tools and pilot lines. Another key project is the “lab to fab accelerator”, which is an instrument to strengthen the transfer of technologies from research institutes to industry, addressing the technology gap.
- Manufacturing Expansion: To reduce reliance on external suppliers, 80 billion euro are planned to be invested in “first-of-a-kind” (FOAK) facilities, which offers innovation that is not yet present in the European Union. Another recommendation is to strengthen Europe’s packaging capabilities by establishing an open-access piloting facility.
Currently, Europe accounts for only 3-4.5% of global electronics packaging. Industry analyst, Yole, predicts that by 2028, advanced packaging will make up more than 50% of packaging revenue, but only 5% of total units. This underscores the high value of advanced packaging and the opportunities for Europe to play a larger role.
Shaping the future of electronics: CEA contribution to 3D integration and 2.5D advanced packaging
Sylvie Joly, 3D Integration and Packaging Partnerships Manager at CEA-Leti, explored how the shift from traditional packaging to system-in-package (SiP) has revolutionized semiconductor integration, allowing for the integration of multiple dies within a single package, enabling greater functionality and miniaturization.
A key aspect of SiP is 3D integration, which allows for high-performance interconnects, increased bandwidth, and energy efficiency. The speaker emphasized that 3D architectures meet modern design needs by reducing form factors, increasing I/O counts, and enabling the reuse of intellectual property (IP) through chiplet structures. Heterogeneous integration further enhances flexibility by combining different CMOS nodes and materials, such as silicon, III-V, and II-VI materials, to create highly specialized applications, including sensor-on-logic and memory-on-logic.
For Europe to stay ahead, advancements in 3D integration are key. Sylvie highlighted two important enabling technologies:
- Through-Silicon Vias (TSV): Enabling vertical interconnects in 3D architectures. There are three types of TSV depending on application: High density TSV, TSV middle and TSV last low density. For SiPs and chiplets, TSV middle is the most commonly used.
- Direct Hybrid Bonding (DHB): A popular bonding technique that can be done on wafer-to-wafer level or die-to-wafer level. The surfaces of the bottom wafer and the top die or wafer, typically consisting of metal pads in a dielectric matrix, are bonded at the molecular level, enabling ultra-dense circuit interconnections.
Sylvie shared insights into CEA-Leti’s roadmap for hybrid bonding, which includes advancements in low-temperature dielectric bonding, reducing die size to 1×1 mm², and achieving finer pitch sizes down to sub-µm for wafer-to-wafer and die-to-wafer bonding.
As a key player in Europe’s five pilot lines dedicated to heterogeneous integration, CEA-Leti is helping to shape the future of semiconductor packaging.
Current Trends in Fan-out Wafer and Panel-level Packaging
Dr. Tanja Braun, Head of System Integration and Interconnection Technologies at Fraunhofer IZM, provided further insights into advanced packaging, specifically highlighting the advancements in fan-out wafer-level packaging (FOWLP) and panel-level packaging (FOPLP).
Fan-out technology continues to evolve, offering cost-effective alternatives for heterogeneous integration. Tanja outlined different process flows, and noted the increasing interest in (redistribution layer (RDL) first and RDL interposer approaches, which are gaining traction due to their potential for cost-effective solutions.
Showing the different approaches to FOWLP for RF applications, Tanja emphasized the importance of packaging being considered alongside chip design. Referring to Steffen’s earlier discussion on design centers, she added that packaging engineers need to work on process design kits (PDKs) for packaging technologies, and that fan-out is a good approach for co-design.
A key innovation she highlighted was the use of bridges—silicon or glass dies that enable local high-density routing to overcome the limitations of organic materials. Tanja speculated that in the future, more Fan-out solutions with mold-embedded bridges will emerge.
Shifting to Panel-Level Packaging (PLP), she explained its potential for cost reduction by increasing area utilization and manufacturing more packages in parallel. Although previous efforts to transition to PLP have faced challenges due to high capital investment requirements, recent trends in HPC and AI are reviving the industry’s interest. The growing demand for large package sizes for AI accelerators and chiplets is a key driver, with companies like TSMC, Samsung, and ASE investing in panel-level capabilities.
Tanja concluded by emphasizing the advantages of Fan-Out PLP for package miniaturization, offering a substrate-less, thermally efficient, high-performance solution. It enables shorter interconnects, passive component integration, and antenna integration for RF applications, making it ideal for System-in-Package (SiP) designs. While PLP presents cost advantages for AI and chiplet applications, it also depends on factors like yield rates and sustainability considerations, such as CO₂ consumption.
Full recording available online
Want to hear the full discussion and explore these presentations in more detail? You can get access to the full recording of the webinar, including Q&A here.
