By Juliana Panchenko and Frank Windrich, Fraunhofer IZM-ASSID
15 years ago, Fraunhofer established the “White House of microelectronics packaging”— a leading-edge research center for 3D integration and advanced wafer-level packaging on 200/300mm wafer sizes. It was founded based on visionary ideas in the field of microelectronic packaging from the former director of Fraunhofer IZM, Prof. Herbert Reichl. Supported by the Free State of Saxony, the Federal Ministry of Education and Research (BMBF) Germany, the European Commission, and the Fraunhofer Society the Center “All Silicon System Integration Dresden – ASSID” was founded directly in the heart of Silicon Saxony in a fully industry compatible clean room environment.
It was the first 300mm R&D facility for this purpose in Germany. The first three years were dedicated to upgrading the “White House” clean room from a back-end chip-scale packaging facility to a leading-edge 3D integration facility, at a time when the mainstream industry was focusing on chip-scale packaging and embedded wafer-level ball-grid array (eWLB) technology.
The focus in the early years of the small, strong, and motivated researcher team was to develop advanced wafer-level packaging technology building blocks in 2.5D / 3D integration. In cooperation with local 300mm foundry partners, through silicon vias (TSV), re-distribution layer (RDL) and micropillar interconnect technologies were developed and transferred to volume production. All required technology building blocks for 2.5D / 3D integration starting from wafer bonding and thinning, multi-layer RDL in Cu damascene and polymer flavor, TSV formation, interconnect fabrication, die assembly, and in-line metrology were set up to form a leading-edge industry-compatible 200/300 mm heterogenous 3D wafer-level system integration pilot line.
The past 15 years have brought numerous scientific projects and industrial cooperations with institutions all over the world. The first years were focused strongly on the above-mentioned topics on the development of Cu TSV processes and 2.5D silicon interposer fabrication with flip-chip micropillar interconnects. A key R&D project was CarrICool leveraging the integration of an active cooled Si interposer with TSVs surrounded by fluidic channels for advanced thermal management in high-performance computing applications (Figure 1)
The expertise in Cu TSV technology opened up the integration of TSVs in custom ASIC devices by TSV’s last 3D integration. Such an integration approach allows leading-edge systems in package (SiPs) for various detector and sensor applications in the medical and industrial fields.
To support the industrial demand for small- and mid-size volume pilot line manufacturing, an ISO 9001 quality system was established in 2014. The middle and end of the decade were focused on extending the wafer-level packaging capabilities to address different markets.
We focused on technology development for RDL1st fan-out wafer-level packaging with multi-die embedding to build highly miniaturized SiPs. The technology was used to develop a universal sensor platform. Furthermore, the integration of Cu/Cu hybrid bonding technology was investigated at a very early stage in the development. Activities to develop the packaging of a full 300 mm wafer-scale integrated high-performance computing system were also realized.
The time is running extremely fast and in semiconductor R&D even faster. Today we see real 3D integration in numerous products driven by the artificial intelligence (AI) and high-performance computing (HPC) market. We see Si interposers in high-volume manufacturing and are in the era of chiplet integration. The industry has wafer-scale computing systems for big data AI applications in the market and we believe that Interconnectology will be the future.
It proves that the decision to start a leading-edge 3D integration research center 15 years ago was absolutely correct. Today’s industry demand for advanced packaging solutions and 3D integration is bigger than ever. The number of microelectronic fabs located in Saxony around Dresden is increasing.
Today, Fraunhofer IZM-ASSID focuses on the fabrication of fine metallization structures to reach back-end-of-line (BEOL) structure sizes and develops new interconnect technologies for high-density assembly, wafer, and chip stacking based on various pitches using Cu/Cu hybrid bonding, microbumps for solid-liquid interdiffusion bonding as well as a new type of interconnect – copper nanowire bump.
Even if many 3D processes have been similar for 15 years, the devil is in the details. Small changes in the process sequence have an enormous influence on the full flow. The “White House” pilot line allows us to investigate these interactions between different technology steps.
Currently, the researchers are seeking new solutions based on chiplets for trusted electronics (Figure 3) and exploring packaging for quantum computing by incorporating new superconductive materials. Moreover, they built a bridge between applied research and academia via a strong scientific cooperation with TU Dresden and established a professorship for nanoelectronics materials in electronic packaging. Now students, PhDs, researchers, and technicians work passionately in a family-like atmosphere of Fraunhofer IZM ASSID.
The upcoming years will bring rapid growth to the “White House of Microelectronics Packaging”. The 3D wafer-level system integration pilot line will be expanded to a 2nd location to extend the 3D technology capabilities. The Center for Advanced CMOS & Heterointegration Saxony was founded with the Fraunhofer IPMS-CNT to bridge the gap for 3D between front-end and back-end wafer-level technology. Among other things, it will accommodate technologies in a 3D bonding hub to support multiple integration schemes for die-to-wafer and wafer-to-wafer system integration. The Center for Heterointegration has been a reality since June 2024!
Additionally, with four major European RTO partners (CEA-Leti, IMEC, VTT, and Fraunhofer), a multi-hub test and experimentation facility for edge AI hardware is in the realization phase. The PREVAIL consortium will allow cross-RTO processing in the field of 3D integration for edge AI applications. Once your design for a 3D system is ready, do not hesitate to come over and fabricate it on a 300mm wafer in the beautiful heart of Silicon Saxony at Fraunhofer IZM-ASSID!
