Broadcom has recently announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP™) platform technology, enabling consumer AI customers to develop next-generation custom accelerators (XPUs).
The new platform relies on TSMC’s CoWoS and other advanced packaging technologies. It will allow designers to build system-in-packages (SiPs) of 3D-stacked logic, network and I/O chiplets, and HBM memory stacks. The platform allows for SiPs with up to 6000mm² of 3D-stacked silicon with 12 HBM modules (Figure 1.) The first 3.5D XDSiP products are set to arrive in 2026. Broadcom’s first F2F 3.5D XPU will integrate four compute dies, one I/O die, and six HBM modules.
Advanced SiP integration is becoming crucial for next-generation XPUs. The computational power required for training generative AI models relies on increasingly sophisticated XPUs to achieve the necessary performance while minimizing power consumption and cost.
Over the past decade, 2.5D integration, has proven valuable for XPU development, however, introducing new and increasingly complex large language models (LLMs) will necessitate 3D silicon stacking for better size, power, and cost. Consequently Broadcom proposes that “3.5D integration”, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.
Broadcom’s 3.5D XDSiP uses TSMC’s CoWoS-L packaging technology that offers a maximum interposer size of approximately 5.5 times that of a reticle (about 858mm2), or 4719mm2 for compute chiplets, I/O chiplets, and up to 12 HBM3/HBM4 packages (Figure 2). To maximize performance, Broadcom suggests disintegrating the design of compute chiplets and stacking one logic chiplet on top of another in a face-to-face (F2F) manner using hybrid copper bonding (HCB) (Figure 3).
Broadcom reports the following Key Benefits:
- Enhanced Interconnect Density: Achieves a 7x increase in signal density between stacked dies compared to F2B technology
- Superior Power Efficiency: Delivers a 10x reduction in power consumption in die-to-die interfaces by utilizing 3D HCB instead of planar die-to-die PHYs
- Reduced Latency: Minimizes latency between compute, memory, and I/O components within the 3D stack
- Compact Form Factor: Enables smaller interposer and package sizes, resulting in cost savings and improved package warpage.
TSMC and Broadcom have collaborated over the past several years to bring together TSMC’s advanced logic processes and 3D chip stacking technologies with Broadcom’s design expertise,
With more than five 3.5D products in development, a majority of Broadcom’s consumer AI customers have adopted the 3.5D XDSiP platform technology with production shipments starting February 2026.
Fujitsu has announced that they will use the technology as the basis of an upcoming server processor with 288 cores. Fujitsu plans to launch its Monaka chip in 2027.
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