This is a call for papers for a special edition of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) on 2.5D/3D chiplets. Topics of interest can be found in the JETCAS Call For Papers.
The objective of this special issue is to give a systematic view of chiplet technology from many aspects, to find possible solutions for challenges, and to compile the latest research findings from researchers in the field.
Scope and Purpose
The task of integrating an increasing number of transistors onto a single chip is becoming increasingly arduous and costly. To counter this challenge, chiplet technology has captured the interest of both industry and academia. A chiplet is a small integrated circuit (IC) with a well-defined function, designed to be incorporated alongside other chiplets within a single package as a multi-die stack. Despite the current interest in a chiplet-based design approach, the associated technology faces numerous challenges that are influencing its development trajectory. This special issue from IEEE is dedicated to showcasing the latest technological advancements in the field of chiplet technology and its applications.
In general, the chiplet interconnects faces design challenges such as achieving high bandwidth, low latency, high energy efficiency, high edge bandwidth density, low bit error rate, etc. There are existing standards for chiplet with no consideration on compatibility with each other at PHY layer specification, this raises the implementation cost of IP vendors and SoC designers.
Designing a chip based on the chiplet approach presents the challenge of how to effectively split a monolithic design into individual chiplets. An improper division will negatively impact the chip’s performance and power efficiency. Furthermore, SoC designers must carefully consider the design of the system bus or I/O connected by chiplet interconnects, and keep the underlying structure remains transparent to the upper-layer software.
When developing a chip based on the chiplet approach, the SoC designer will meet the lack of comprehensive EDA tool coverage from front-end to back-end. For example, there are no EDA tools for multi-chiplets co-simulation in the front-end phase. They must leverage existing EDA tools that were initially designed for the development of monolithic SoC designs. Although multi-physics field co-simulation is utilized to identify potential risks before the tape-out phase, it is more beneficial and cost-effective to detect and mitigate issues during the front-end phase.
While chiplets are typically considered to be connected by interposers in advanced packaging, new methods such as silicon bridges have garnered public attention due to their lower cost. Hybrid bonding is also emerging as a promising technique for its extremely high density. 3D stacked ICs based on the chiplet approach draw more attention for their efficient way to integrate functional chiplets, but also result in more problems such as thermal.
2.5D- and 3D-stacked ICs based on the chiplet approach have many more potential test moments than conventional chips. Every test that is executed adds cost, and therefore, executing all these tests might lead to overkill and excessive test costs. However, not executing tests could lead to even higher costs. At the same time, pre-bond testing of the non-bottom dies is a challenging task, and we need to rely on a cooperative design-for-test infrastructure in the die-under-test and all dies below it.
Submission Procedure
Prospective authors are invited to submit their papers following the instructions provided on the IEEE JETCAS website. The submitted manuscripts should not have been previously published, nor should they be currently under consideration for publication elsewhere. See the IEEE JETCAS submission site for more information.
Important Dates
- Manuscript submissions due: March 03, 2025
- First round of reviews completed: April 21, 2025
- Revised manuscripts due: June 02, 2025
- Second round of reviews completed: June 30, 2025
- Final manuscripts due: July 21, 2025
- Request for information Corresponding Guest Editor: Qinfen Hao (haoqinfen@ict.ac.cn)
