TSMC/Amkor agreement Will Put U.S. Advanced Packaging on The Map
TSMC has signed a memorandum of understanding (MoU) with Amkor Technology. Under the agreement, Amkor will provide TSMC with turnkey advanced packaging and test services from its planned assembly and test company plant in Peoria, Arizona.
Both TSMC and Amkor have been awarded funding from the U.S. government under the CHIPS and Science Act to support the construction of their Arizona plants. As readers of IFTLE all know, TSMC is building three fabs in Phoenix, Arizona, two of which will produce 4nm and 3nm semiconductors, and a third will manufacture 2nm chips. In April, the Department of Commerce announced it would be awarding TSMC a funding package of $11.6B, consisting of $6.6B in grants and an additional $5B in loans.
Amkor is set to receive up to $400MM in direct funding and $200MM in loans from the CHIPS Act to support the company’s reported $2B investment in the proposed OSAT plant. The facility would be the largest OSAT facility in the US.
In November 2023, Apple signed a deal with Amkor to package its Apple Silicon at the Peoria facility, which TSMC will produce at its nearby Phoenix fab. Therefore, it was only logical that the relationship between TSMC and Amkor would expand to include Amkor packaging TSMCs other advanced node chips for other US customers.
The two companies said “the close collaboration and proximity of TSMC’s front-end fab and Amkor’s back-end facility will accelerate overall product cycle times,” adding that they will “jointly define the specific packaging technologies” used to address common customer needs, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS) that will be employed to address common customers’ needs.
Since the announcement of the TSMC AZ facilities, it has only been logical that a source of chip packaging also had to be part of the plan. Surely, even Washington politicians would eventually see that making state-of-the-art (SOTA) chips without matching packaging capability would be an embarrassing situation for the CHIPS Act.
So…. what else can we posit from what we now know?
Well for one thing we know that these SOTA chips from TSMC’s AZ fab will have to be bumped – probably copper pillar bumped (CPB) – and once again it will make no sense to be sending them back to Taiwan to get that done. So… one could once again expect TSMC to be doing this themselves (they already do in house bumping in Taiwan) or lean on Amkor (one of the world’s leading bumping houses) to handle this for them.
One more linkage for you…… Recall that Unitive bumping, and its plated bump process, was spun out of the Microelectronics Center of North Carolina (now known as Micross) and then acquired by Amkor? So, the Micross and the Amkor bumping processes are, let’s say, very similar. Thus, the new Micross 300mm bumping line, being funded by the IBAS RESHAPE program under Matt Walsh, could actually be considered a second source for bumping of TSMC chips. Will that happen? I guess we will just have to wait and see!
IMAPS 2024 – Onshoring Fosters U.S. Advanced Packaging
The IMAPS annual meeting was held the first week of October in Boston with Tarak Railkar as General Chair. The conference included 15 professional development courses, 95 exhibitors, 6 Keynote talks including Dev Palmer now head of the CHIPS Act’s National Advanced Packaging Manufacturing Project (NAPMP).
There were two special panel sessions held on the afternoon before the official conference opening. Session One concerned “Onshoring High Density Interposers and Fan-out WLP/PLPs” The panelists, shown in Figure 1 included (L to R) session chair Brandon Hamilton (BAE), John Lannon (Micross), Dave Howard (Tower Semi), Alan Huffman (Skywater), Bob Patti (Nhanced Semicondoctor), Tim Olson (Deca), Matt Walsh (Navy Crane- IBAS), and Dale McHerron (IBM).
Session 2 dealt with “Onshoring High Density Advanced Packaging PWBs”. Panelists included (L to R): session chair Brandon Hamilton (BAE), Dave Reichert (DuPont), Michael Gleason (Greensource), session chair Steve Dooley (AFRL), Dave Shahin (NG), Meridith Labeau (Calumet), Sylvain Pharand (IBM), and Alan Boone (BAE).
IFTLE is personally not a fan of panel sessions. Everyone was told to have only two slides and spend only 5 minutes introducing their company, but nearly all of them ignored the instructions and wasted half of the session telling us things about their companies that most attendees already knew. Then the questions from the audience came and mostly got trivial responses. Anyway… when I searched for anything new and important that was said I came up with the following:
- Skywater noted that its Florida Deca line should be ready for sampling / low volume production in 2026.
- IBM indicated that it would be scaling up a modified version of the Deca process in Bromont soon…McHerron also said he thought there would be lots of US-based Deca-like offerings available onshore in the next five years.
- DuPont announced two build-up film (BUF) products were in its pipeline. These will hopefully be used to produce high-density build-up in the US.
IMAPS 2024 Keynote- Dev Palmer
Dev Palmer, now Director of CHIPS NAPMP announced that they hoped to stand up four baseline processes at National Advanced Packaging Pilot Facility (NAPPF) .
He also announced that the Notice of Funding Opportunity (NOFO) for the remaining five technology areas for NAPMP will all be released all at once. The announcement came October 18, 2024 and is available here.
The five remaining areas are:
- Equipment, tools, and processes
- Power delivery and thermal management for advanced packaging assemblies
- Photonics and connectors that communicate with the outside world
- A chiplet ecosystem
- Co-design of multi-chiplet systems with automated tools
CHIPS for America anticipates making available up to approximately $1.6 billion in funding across multiple awards of varying size and scope. Anticipated amounts will vary by R&D area and range from approximately $10 million to approximately $150 million in Federal funds per award, with awards being made over a five-year period of performance. Additionally, CHIPS for America anticipates reserving up to $50 million to support awardees’ future prototyping activities, to be conducted at the anticipated National Semiconductor Technology Center (NSTC) Prototyping and NAPMP Advanced Packaging Piloting Facility.
On October 22, 2024, the CHIPS Research and Development Office hosted a one-day meeting for potential applicants to this funding opportunity, followed by on-demand webinars explaining each research and development area.
For all the latest in Advanced Packaging stay linked to IFTLE…………………………..
